Abstract: A cache structure implemented in a microprocessor core include a set predictor and a logical directory. The set predictor contains a plurality of predictor data sets containing cache line information, and outputs a first set-ID indicative of an individual predictor data set. The logical directory contains a plurality of logical data sets containing cache line information. The cache structure selectively operates in a first mode such that the logical directory receives the first set-ID that points to an individual logical data set, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set. The logical directory performs a cache lookup based on the first set-ID in response to operating in the first mode, and performs a cache lookup based on the second set-ID in response to operating in the second mode.

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

Abstract: A cache structure implemented in a microprocessor core include a set predictor and a logical directory. The set predictor contains a plurality of predictor data sets containing cache line information, and outputs a first set-ID indicative of an individual predictor data set. The logical directory contains a plurality of logical data sets containing cache line information. The cache structure selectively operates in a first mode such that the logical directory receives the first set-ID that points to an individual logical data set, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set. The logical directory performs a cache lookup based on the first set-ID in response to operating in the first mode, and performs a cache lookup based on the second set-ID in response to operating in the second mode.

Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

Abstract: Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.

Abstract: Embodiments include optimizing the grouping of instructions in a microprocessor. Aspects include receiving a first clump of instructions from a streaming buffer, pre-decoding each of instructions for select information and sending the instructions to an instruction queue. Aspects further include storing initial grouping information for the instructions in a local register, wherein the initial grouping information is based on the select information. Aspects further include updating the initial group information stored in the local register when additional pre-decode information becomes available and grouping the instructions that are ready to be dispatched into a dispatch group based on the grouping information stored in the local register. Aspects further include dispatching the dispatch group to an issue unit.