Abstract: Systems and methods for frictionless payments in Web 3.0 and the Metaverse are disclosed. A method may include a buyer bot: monitoring a buyer interaction with a merchant of a digital collectable via a buyer vault/digital wallet, the digital collectable having a cryptocurrency price in a cryptocurrency; determining a fiat currency price in a fiat currency for the cryptocurrency price; receiving, from the buyer vault/digital wallet, conformation of a purchase of the digital collectable at the fiat currency price; executing payment for the digital collectable in the fiat currency at the fiat currency price; transforming the payment in the fiat currency to a digital collectable concierge service designated account; engaging a fiat-to-crypto on-ramp to convert the fiat currency to the cryptocurrency; and providing the payment in the cryptocurrency to a digital collectable smart contract that mints or delivers the digital collectable to the buyer.

Abstract: Active semiconductor devices in an integrated circuit are provided lateral electrical isolation by surrounding narrow deep trench isolation regions that are merged at shared portions of the narrow deep trench isolation regions. A wide deep trench isolation region laterally surrounds the merged narrow deep trench isolation regions.

Abstract: The present disclosure relates to devices, circuits, and methods of determining power consumption in an electronic device (e.g., HDD) so that the determined power consumption can be used to determine a concentration of the gaseous oxidizing agent component in an interior gas space of the sealed enclosure and/or actively supply gaseous oxidizing agent component to the interior gas space of the electronic device if the determined power consumption is below a threshold value.

Abstract: The present invention discloses a magnetically driven portable multi-cell separation device. According to one embodiment of the present invention, the magnetically driven portable multi-cell separation device includes: A microscope capable of nano-scale observation, A chip unit, positioned below the microscope, enabling selective cell sorting and capture, A magnetic field generator, which is adjacent to the chip unit and can control the magnetic field via a magnetic member, and A control unit, which controls the operation of the imaging unit, the chip unit, and the magnetic field generator.

Abstract: The present disclosure generally relates to semiconductor processing for forming a semiconductor device. In an example, semiconductor device includes a semiconductor substrate, a nitride structure, and an oxide layer. The nitride structure is over the semiconductor substrate. The oxide layer is on the nitride structure. The semiconductor substrate includes an implanted doped region laterally proximate the nitride structure and the oxide layer. In another example, a nitride structure is formed over a semiconductor substrate. An oxide layer is formed on the nitride structure. A photoresist is formed over the semiconductor substrate. The photoresist has an opening exposing at least a portion of the oxide layer on the nitride structure. An implantation is performed using the photoresist to form an implanted doped region in the semiconductor substrate.

Abstract: An integrated circuit includes a bipolar transistor extending into a [100] surface of a semiconductor substrate having a crystalline lattice. A deep trench surrounds the bipolar transistor and has a path having a plurality of sides. At least one side extends in a direction parallel to a <100> axis of the crystalline lattice.

Abstract: An integrated circuit includes a gate electrode over a silicon substrate and a local oxidation of silicon (LOCOS) structure between the gate electrode and the silicon substrate. The LOCOS structure has bird's beak portions, peripheral portions between the bird's beak portions, and a central portion between the peripheral portions. The peripheral portions have a first thickness, and the central portion has a greater second thickness.

Abstract: A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.

Abstract: An integrated circuit includes a fin field-effect transistor (FinFET). The FinFET has a semiconductor fin located over a substrate, the semiconductor fin including a source region, a body region, a drift region, and a drain region. The semiconductor fin has a top surface and sidewalls. A field plate insulator is over the top surface and the sidewalls of the drift region. The drift region is doped with a first dopant and a second dopant, a concentration of the first dopant being greater at the top surface and a concentration of the second dopant being greater at the sidewalls.

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Abstract: A heat dissipation device with a heat-insulating channel includes a thermal conductive substrate, multiple heat dissipation fins stacked with spacing from one another on the thermal conductive substrate, and at least one insulation guiding component. The heat dissipation fins have at least one configuration space for the insulation guiding component to be installed, a bottom portion, two sides upwardly extended from the bottom portion, and a channel enclosed by the bottom portion and two sides. A width of the channel is at least greater than the spacing between any two adjacent heat dissipation fins.

Abstract: A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.

Abstract: Described examples include an integrated circuit including a dielectric layer located over a top surface of a semiconductor substrate and extending over a gate electrode. A trench extends from a top surface of the dielectric layer into the substrate. A conductive trench electrode is within the trench, and a dielectric liner is between the trench electrode and the semiconductor substrate. A cap dielectric layer is located on the conductive trench electrode and on the dielectric layer, and extends over the gate electrode.

Abstract: A method of fabricating an integrated circuit includes forming and patterning a hardmask over a substrate such that the patterned hardmask exposes regions of the substrate. The exposed regions are etched, thereby forming trenches and a semiconductor fin between the trenches. Prior to removing the hardmask, a photoresist layer is formed and patterned, thereby exposing a section of the semiconductor fin. A dopant is implanted into the exposed section through the hardmask.

Abstract: A heat dissipation device with a heat-insulating channel includes a thermal conductive substrate, multiple heat dissipation fins stacked with spacing from one another on the thermal conductive substrate, and at least one insulation guiding component. The heat dissipation fins have at least one configuration space for the insulation guiding component to be installed, a bottom portion, two sides upwardly extended from the bottom portion, and a channel enclosed by the bottom portion and two sides. A width of the channel is at least greater than the spacing between any two adjacent heat dissipation fins.

Abstract: A vapor chamber supporting capillary structure includes a first plate, a second plate and a capillary layer. The capillary layer is clamped between the first plate and the second plate and includes a first capillary portion and a second capillary portion. The second capillary portion is connected to the first capillary portion and extends outward, and a notch is formed at any one side of the second capillary portion. The notch is formed along an extension direction of the second capillary portion. Furthermore, the first plate includes a plurality of capillary supporting structures and a plurality of plate supporting structures formed thereon, and the capillary supporting structures are corresponding to the first capillary portion and the second capillary portion, and the plate supporting structures are corresponding to the notch. Accordingly, a greater steam space may be obtained.

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

Abstract: In some aspects, the techniques described herein relate to a method including: providing, on a peer-to-peer distributed network, an aggregation server; implementing, at a first node of the peer-to-peer distributed network, a machine learning (ML) model, wherein the ML model is trained on a first private data set; sending the ML model to the aggregation server; replicating the ML model to a second node of the peer-to-peer distributed network, wherein the ML model is retrained on a second private data set to generate a retrained model; sending the retrained model to the aggregation server; aggregating the ML model and the retrained model to generate an aggregated model; and replicating the aggregated model to the first node of the peer-to-peer distributed network, wherein the ML model is promoted to a production model at the first node of the peer-to-peer distributed network.

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.