Abstract: An automotive processing unit includes an infotainment system having a speech interface, an application suite comprising one or more spatially-cognizant applications, and an automotive assistant that is configured to execute one or more of the spatially-cognizant applications. The speech interface is configured to receive a navigation announcement from a navigator and a touring announcement from one of the spatially-cognizant applications and, in response, to cause a spoken announcement to be made audible in a vehicle's cabin through a loudspeaker. The spoken announcement comprising content from at least one of the touring announcement and the navigation announcement.

Abstract: A heat dissipation device with a heat-insulating channel includes a thermal conductive substrate, multiple heat dissipation fins stacked with spacing from one another on the thermal conductive substrate, and at least one insulation guiding component. The heat dissipation fins have at least one configuration space for the insulation guiding component to be installed, a bottom portion, two sides upwardly extended from the bottom portion, and a channel enclosed by the bottom portion and two sides. A width of the channel is at least greater than the spacing between any two adjacent heat dissipation fins.

Abstract: A vapor chamber supporting capillary structure includes a first plate, a second plate and a capillary layer. The capillary layer is clamped between the first plate and the second plate and includes a first capillary portion and a second capillary portion. The second capillary portion is connected to the first capillary portion and extends outward, and a notch is formed at any one side of the second capillary portion. The notch is formed along an extension direction of the second capillary portion. Furthermore, the first plate includes a plurality of capillary supporting structures and a plurality of plate supporting structures formed thereon, and the capillary supporting structures are corresponding to the first capillary portion and the second capillary portion, and the plate supporting structures are corresponding to the notch. Accordingly, a greater steam space may be obtained.

Abstract: A method of making an aluminum-cubic boron nitride (Al-cBN) composite includes mixing an aluminum powder and particles of cubic boron nitride (cBN) in a solvent and sonicating to form an Al-cBN mixture; drying the Al-cBN mixture to form a dried mixture powder; and sintering by pressing and heating the dried mixture powder to form the Al-cBN composite. The aluminum powder has an average particle size of 10 to 100 micrometers (?m). The cBN particles have an average particle size of from 10 to 100 ?m, and are uniformly dispersed throughout the Al-cBN composite.

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

Abstract: In some aspects, the techniques described herein relate to a method including: providing, on a peer-to-peer distributed network, an aggregation server; implementing, at a first node of the peer-to-peer distributed network, a machine learning (ML) model, wherein the ML model is trained on a first private data set; sending the ML model to the aggregation server; replicating the ML model to a second node of the peer-to-peer distributed network, wherein the ML model is retrained on a second private data set to generate a retrained model; sending the retrained model to the aggregation server; aggregating the ML model and the retrained model to generate an aggregated model; and replicating the aggregated model to the first node of the peer-to-peer distributed network, wherein the ML model is promoted to a production model at the first node of the peer-to-peer distributed network.

Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

Abstract: Forming an integrated circuit by first, forming a first fin and a second fin from a semiconductor layer, with an area between the first fin and the second fin, second, forming a dielectric layer covering at least a portion of the first fin, at least a portion of the second fin, and at least a portion of the area, and third, forming amorphous polysilicon covering a least a portion of the dielectric layer.

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Abstract: A method of forming an integrated circuit includes forming a plurality of openings in a resist layer over a semiconductor substrate and removing portions of a semiconductor surface layer exposed by the openings, thereby forming a plurality of deep trenches. Removing the portions includes performing a first etch loop for a first plurality of repetitions, the first etch loop including a deposition process executed for a first deposition time and an etch process executed for a first etch time. The removing further includes performing a second etch loop for a second plurality of repetitions, the second etch loop including the deposition process executed for a second deposition time and an etch process executed for a second etch time. The second deposition time is at least 10% greater than the first deposition time, and the second etch time is at least 10% greater than the first etch time.

Abstract: Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

Abstract: Systems and methods are disclosed for monitoring power usage and temperature within a data storage device, and adjusting performance based on the power usage and temperature. In certain embodiments, an apparatus may comprise a data storage device (DSD) having an interface to communicate with a host device, and a circuit. The circuit may be configured to receive a first limit designation for a first operating parameter of the DSD via the interface, monitor a value of the first operating parameter of the DSD, evaluate a pending workload of operations to be performed by the DSD, estimate a future value of the first operating parameter based on the pending workload, and adjust performance of the DSD based on the future value and the first limit designation.

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Abstract: Active semiconductor devices in an integrated circuit are provided lateral electrical isolation by surrounding narrow deep trench isolation regions that are merged at shared portions of the narrow deep trench isolation regions. A wide deep trench isolation region laterally surrounds the merged narrow deep trench isolation regions.

Abstract: A passive circuit component includes an edge having a low line edge roughness (LER). A method for manufacturing the passive circuit component includes a self-aligned double patterning (SADP) etch process using a tri-layer process flow. The tri-layer process flow includes use of an underlayer, hard mask, and photoresist. The passive circuit component made by this method achieves improved mismatch between like components due to the low LER.

Abstract: The present disclosure relates to devices, circuits, and methods of determining power consumption in an electronic device (e.g., HDD) so that the determined power consumption can be used to determine a concentration of the gaseous oxidizing agent component in an interior gas space of the sealed enclosure and/or actively supply gaseous oxidizing agent component to the interior gas space of the electronic device if the determined power consumption is below a threshold value.

Abstract: Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.

Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.