Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

Abstract: A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

Abstract: Systems and methods are disclosed for monitoring power usage and temperature within a data storage device, and adjusting performance based on the power usage and temperature. In certain embodiments, an apparatus may comprise a data storage device (DSD) having an interface to communicate with a host device, and a circuit. The circuit may be configured to receive a first limit designation for a first operating parameter of the DSD via the interface, monitor a value of the first operating parameter of the DSD, evaluate a pending workload of operations to be performed by the DSD, estimate a future value of the first operating parameter based on the pending workload, and adjust performance of the DSD based on the future value and the first limit designation.

Abstract: Natural products were screened for their insect repellent activity, and carrot seed essential oil gave very high activity in biting repellent/deterrent bioassays. Analysis of the oil revealed the presence of 47 compounds, mainly mono- and sesqui-terpenes. The sesquiterpene, carotol, constituted more than 75% w/w of the oil. In the initial screening, the essential oil gave high biting deterrent activity and high repellent activity comparable to DEET against both Aedes aegypti and Anophies quadrimaculatus species of mosquitoes. The active fraction mainly comprises pure carotol. The essential oil and the pure compound have a potential to be developed and used as effective repellent against mosquitoes.

Abstract: A method including obtaining x-ray data for a multi-component object; processing the x-ray data to obtain at least first and second 3D representations of the object with respective first and second resolutions, the first resolution being higher than the second resolution; identifying a plurality of regions of the second 3D representation, each region corresponding to one of a number of components of the object, by at least identifying a number of initial regions of the second 3D representation, each initial region having pixel values in one of a plurality of ranges of pixel values, and adjusting each of the number of initial regions based on a comparison between the initial region and features derived from 2D sections of the object from the first 3D representation; and obtaining a 3D model.

Abstract: A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

Abstract: A method includes processing, via an integrated circuit, data read from a first servo wedge; processing, via the integrated circuit, data from a second servo wedge; and skipping processing data from a third servo wedge positioned between the first servo wedge and the second servo wedge.

Abstract: A semiconductor device with an isolation structure and a trench capacitor, each formed using a single resist mask for etching corresponding first and second trenches of different widths and different depths, with dielectric liners formed on the trench sidewalls and polysilicon filling the trenches and deep doped regions surrounding the trenches, including conductive features of a metallization structure that connect the polysilicon of the isolation structure trench to the deep doped region to form an isolation structure.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.

Abstract: An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.

Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

Abstract: An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.

Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

Abstract: Natural products were screened for their insect repellent activity, and carrot seed essential oil gave very high activity in biting repellent/deterrent bioassays. Analysis of the oil revealed the presence of 47 compounds, mainly mono- and sesqui-terpenes. The sesquiterpene, carotol, constituted more than 75% w/w of the oil. In the initial screening, the essential oil gave high biting deterrent activity and high repellent activity comparable to DEET against both Aedes aegypti and Anophies quadrimaculatus species of mosquitoes. The active fraction mainly comprises pure carotol. The essential oil and the pure compound have a potential to be developed and used as effective repellent against mosquitoes.

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer, at least one capacitor above the semiconductor surface layer including a bottom plate, a capacitor dielectric over the bottom plate, and a top plate over the capacitor dielectric, functional circuitry in the semiconductor surface layer includes a core region having transistors configured together with the capacitor for realizing at least one circuit function. Electrically conductive metal filled contacts are through the dielectric layer that contact the top plate, the bottom plate, and the core region, including a first filled contact hole having a first depth and a first width that reach the top capacitor plate, and second filled contact hole having a second depth and a second width that reach the core region. The second depth is deeper than the first depth, and the first width is at least ten (10) % larger than the second width.

Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.