Patents by Inventor Abdellatif Bellaouar

Abdellatif Bellaouar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312603
    Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ? the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ? the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ? the first frequency or about ? the second frequency during the duty cycle.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 10, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Sher Jiun Fang, Frank Zhang
  • Patent number: 10432179
    Abstract: We disclose frequency doublers for use in millimeter-wave devices. One such frequency doubler comprises at least one passive mixer comprising at least one of the following: at least one transistor configured to receive a back gate voltage; at least one first input driver circuit; and two second input driver circuits. We also disclose a method comprising determining a target output voltage of a frequency doubler comprising at least one passive mixer comprising at least one transistor configured to receive a back gate voltage; determining an output voltage of the frequency doubler; increasing a back gate voltage of the at least one transistor, in response to determining that the output voltage is below the target output voltage; and decreasing the back gate voltage of the at least one transistor, in response to determining that the output voltage is above the target output voltage.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Publication number: 20190296700
    Abstract: In an exemplary structure, a transformer has a primary side and a secondary side. Output from the primary side is coupled to the secondary side. A first power supply is connected to a center tap of the primary side of the transformer. An oscillator includes a first transistor and a second transistor. The front-gate of the first transistor is connected to the drain of the second transistor and the primary side of the transformer. The front-gate of the second transistor is connected to the drain of the first transistor and the primary side of the transformer. A third transistor is connected to the first transistor and a fourth transistor is connected to the second transistor. The third and fourth transistors inject a desired frequency to the oscillator. A voltage source is connected to the back-gate of the first transistor and the back-gate of the second transistor.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: See T. Lee, Abdellatif Bellaouar
  • Publication number: 20190296720
    Abstract: We disclose frequency doublers for use in millimeter-wave devices. One such frequency doubler comprises at least one passive mixer comprising at least one of the following: at least one transistor configured to receive a back gate voltage; at least one first input driver circuit; and two second input driver circuits. We also disclose a method comprising determining a target output voltage of a frequency doubler comprising at least one passive mixer comprising at least one transistor configured to receive a back gate voltage; determining an output voltage of the frequency doubler; increasing a back gate voltage of the at least one transistor, in response to determining that the output voltage is below the target output voltage; and decreasing the back gate voltage of the at least one transistor, in response to determining that the output voltage is above the target output voltage.
    Type: Application
    Filed: March 22, 2018
    Publication date: September 26, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Publication number: 20190288646
    Abstract: We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.
    Type: Application
    Filed: May 31, 2019
    Publication date: September 19, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Publication number: 20190267946
    Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.
    Type: Application
    Filed: March 27, 2019
    Publication date: August 29, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Shafiullah Syed, Abdellatif Bellaouar, Chi Zhang
  • Patent number: 10355646
    Abstract: We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Publication number: 20190190446
    Abstract: A CMOS gain element is disclosed herein. Also disclosed herein are splitters, comprising the CMOS gain element, and local oscillator distribution circuitry comprising the splitters and the CMOS gain elements. Semiconductor devices comprising the local oscillator distribution circuitry may have smaller footprints and reduced power consumption relative to prior art devices.
    Type: Application
    Filed: April 30, 2018
    Publication date: June 20, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan
  • Publication number: 20190190453
    Abstract: We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.
    Type: Application
    Filed: April 30, 2018
    Publication date: June 20, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Patent number: 10326420
    Abstract: We disclose a receiver circuit which may be used in mm-wave devices. The receiver circuit comprises a transimpedance amplifier comprising PMOS and NMOS transistors, wherein the back gate voltages provided to the transistors may be adjusted. By adjusting the back gate voltages during device operation, structural variations and temperature variations in the threshold voltages of the transistors may be minimized and the gain compression tolerance of the receiver circuit may be increased.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Mehmet Ipek, Frank Zhang
  • Patent number: 10291183
    Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shafiullah Syed, Abdellatif Bellaouar, Chi Zhang
  • Patent number: 10211825
    Abstract: Electronic circuits with a switch and methods for operating a switch in an electronic circuit. A first amplifier is coupled by a first path with an antenna. A second amplifier is coupled by a second path with the antenna. A transistor is coupled with the first path at a node. The first transistor includes a back gate. A back-gate bias circuit is coupled with the back gate of the first transistor. The back-gate bias circuit is configured to supply a bias voltage to the back gate of the first transistor that lowers a threshold voltage of the transistor.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Abdellatif Bellaouar
  • Publication number: 20180358962
    Abstract: Electronic circuits with a switch and methods for operating a switch in an electronic circuit. A first amplifier is coupled by a first path with an antenna. A second amplifier is coupled by a second path with the antenna. A transistor is coupled with the first path at a node. The first transistor includes a back gate. A back-gate bias circuit is coupled with the back gate of the first transistor. The back-gate bias circuit is configured to supply a bias voltage to the back gate of the first transistor that lowers a threshold voltage of the transistor.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 13, 2018
    Inventor: Abdellatif Bellaouar
  • Publication number: 20180269868
    Abstract: A method of circuit tuning, including: applying a first positive voltage and a second positive voltage to a circuit structure, the circuit structure including a p-type metal-oxide semiconductor (PMOS) device with a flipped well transistor and an n-type metal-oxide semiconductor (NMOS) device; adjusting a first threshold voltage in response to the first positive voltage being applied to a p-well region of the NMOS device and adjusting a second threshold voltage in response to the second positive voltage being applied to the p-well region of the PMOS device; and compensating the first threshold voltage and the second threshold voltage through a backgate of the PMOS device and the NMOS device relative to a same common mode voltage.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 20, 2018
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan
  • Patent number: 10079597
    Abstract: A method of circuit tuning, including: applying a first positive voltage and a second positive voltage to a circuit structure, the circuit structure including a p-type metal-oxide semiconductor (PMOS) device with a flipped well transistor and an n-type metal-oxide semiconductor (NMOS) device; adjusting a first threshold voltage in response to the first positive voltage being applied to a p-well region of the NMOS device and adjusting a second threshold voltage in response to the second positive voltage being applied to the p-well region of the PMOS device; and compensating the first threshold voltage and the second threshold voltage through a backgate of the PMOS device and the NMOS device relative to a same common mode voltage.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: September 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan
  • Patent number: 10038413
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Taur Lee, Abdellatif Bellaouar
  • Patent number: 10014828
    Abstract: Embodiments of the present disclosure provide a transmitter system including: a source follower (SF) sub-stage having a pair of transistors, one being coupled to a biasing voltage at a gate terminal thereof, and the other including a fully depleted semiconductor on insulator (FDSOI) transistor coupled to an input signal at a gate terminal thereof, and coupled to a calibration voltage at a back-gate terminal thereof. A mixer sub-stage includes a mixer input node coupled to the SF output node of the pair of transistors of the SF sub-stage, and the mixer input node is electrically coupled in parallel to two FDSOI mixer transistors, with the FDSOI mixer transistor being electrically coupled to a respective back-gate voltage. The FDSOI mixer transistors each include a gate terminal coupled to an input voltage, while a second source/drain terminal of the FDSOI mixer transistors are each electrically coupled to a mixer output node.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: See Lee, Abdellatif Bellaouar
  • Publication number: 20180167038
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventors: See Taur LEE, Abdellatif BELLAOUAR
  • Patent number: 9831838
    Abstract: A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 28, 2017
    Assignee: Nvidia Corporation
    Inventors: Sherif Abdelhalem, Frank Zhang, Abdellatif Bellaouar, Sherif Embabi
  • Patent number: 9806701
    Abstract: A transformer-less DFM device comprising: an input receiving signals that are an integer multiple of an input signal; an edge detector that provides a quantized or a state output comparing an the input signal to a feedback signal; a statemachine that has counters and decimation circuits to provide a digitized output to a DAC that tunes delays between the input/output signals; a DLL for generating delay signals from the input signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a multiplied output signal; a first DAC that takes the signal from the statemachine and provide a control to a supply circuit of the DLL to adjust a delay through a supply voltage; a second DAC that takes a signal from the statemachine and provides control to a backgate circuit of the DLL to adjust the delay.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Abdellatif Bellaouar, Arul Balasubramaniyan