Abstract: We disclose a receiver circuit which may be used in mm-wave devices. The receiver circuit comprises a transimpedance amplifier comprising PMOS and NMOS transistors, wherein the back gate voltages provided to the transistors may be adjusted. By adjusting the back gate voltages during device operation, structural variations and temperature variations in the threshold voltages of the transistors may be minimized and the gain compression tolerance of the receiver circuit may be increased.

Abstract: An apparatus, comprising an input transformer; a first differential transistor pair configured to receive a first back gate bias voltage; a second differential transistor pair configured to receive a second back gate bias voltage; a cross-coupled neutralization cap comprising PMOS or NMOS transistors and configured to receive a third back gate bias voltage; and an output transformer. A method of fixing at least one back gate bias voltage to impart a desired capacitance to the transistors of at least one of the first differential transistor pair, the second differential transistor pair, or the neutralization cap. The apparatus and method may provide a power amplifier having improved linearity and efficiency.

Abstract: Electronic circuits with a switch and methods for operating a switch in an electronic circuit. A first amplifier is coupled by a first path with an antenna. A second amplifier is coupled by a second path with the antenna. A transistor is coupled with the first path at a node. The first transistor includes a back gate. A back-gate bias circuit is coupled with the back gate of the first transistor. The back-gate bias circuit is configured to supply a bias voltage to the back gate of the first transistor that lowers a threshold voltage of the transistor.

Abstract: Electronic circuits with a switch and methods for operating a switch in an electronic circuit. A first amplifier is coupled by a first path with an antenna. A second amplifier is coupled by a second path with the antenna. A transistor is coupled with the first path at a node. The first transistor includes a back gate. A back-gate bias circuit is coupled with the back gate of the first transistor. The back-gate bias circuit is configured to supply a bias voltage to the back gate of the first transistor that lowers a threshold voltage of the transistor.

Abstract: A method of circuit tuning, including: applying a first positive voltage and a second positive voltage to a circuit structure, the circuit structure including a p-type metal-oxide semiconductor (PMOS) device with a flipped well transistor and an n-type metal-oxide semiconductor (NMOS) device; adjusting a first threshold voltage in response to the first positive voltage being applied to a p-well region of the NMOS device and adjusting a second threshold voltage in response to the second positive voltage being applied to the p-well region of the PMOS device; and compensating the first threshold voltage and the second threshold voltage through a backgate of the PMOS device and the NMOS device relative to a same common mode voltage.

Abstract: A method of circuit tuning, including: applying a first positive voltage and a second positive voltage to a circuit structure, the circuit structure including a p-type metal-oxide semiconductor (PMOS) device with a flipped well transistor and an n-type metal-oxide semiconductor (NMOS) device; adjusting a first threshold voltage in response to the first positive voltage being applied to a p-well region of the NMOS device and adjusting a second threshold voltage in response to the second positive voltage being applied to the p-well region of the PMOS device; and compensating the first threshold voltage and the second threshold voltage through a backgate of the PMOS device and the NMOS device relative to a same common mode voltage.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.

Abstract: Embodiments of the present disclosure provide a transmitter system including: a source follower (SF) sub-stage having a pair of transistors, one being coupled to a biasing voltage at a gate terminal thereof, and the other including a fully depleted semiconductor on insulator (FDSOI) transistor coupled to an input signal at a gate terminal thereof, and coupled to a calibration voltage at a back-gate terminal thereof. A mixer sub-stage includes a mixer input node coupled to the SF output node of the pair of transistors of the SF sub-stage, and the mixer input node is electrically coupled in parallel to two FDSOI mixer transistors, with the FDSOI mixer transistor being electrically coupled to a respective back-gate voltage. The FDSOI mixer transistors each include a gate terminal coupled to an input voltage, while a second source/drain terminal of the FDSOI mixer transistors are each electrically coupled to a mixer output node.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a fully depleted silicon on insulator power amplifier with unique biases and voltage standing wave ratio protection and methods of manufacture. The structure includes a pseudo-differential common source amplifier; first stage cascode devices connected to the pseudo-differential common source amplifier and protecting the pseudo-differential common source amplifier from an over stress; second stage cascode devices connected to the first stage cascode devices and providing differential outputs; and at least one loop receiving the differential outputs from the second stage cascode devices and feeding back the differential outputs to the second stage cascode devices.

Abstract: A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

Abstract: A transformer-less DFM device comprising: an input receiving signals that are an integer multiple of an input signal; an edge detector that provides a quantized or a state output comparing an the input signal to a feedback signal; a statemachine that has counters and decimation circuits to provide a digitized output to a DAC that tunes delays between the input/output signals; a DLL for generating delay signals from the input signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a multiplied output signal; a first DAC that takes the signal from the statemachine and provide a control to a supply circuit of the DLL to adjust a delay through a supply voltage; a second DAC that takes a signal from the statemachine and provides control to a backgate circuit of the DLL to adjust the delay.

Abstract: Disclosed is an amplifier circuit having a single-ended input and differential outputs. The differential outputs are achieved using a first output branch and a second output branch, each including a common source FET (CS-FET) and a common gate FET (CG-FET) connected in series between ground and a corresponding out node connected to a load. An input signal is applied to the CS-FET in the first output branch and an intermediate signal at an intermediate node between the CS-FET and the CG-FET in the first output branch is applied to the CS-FET in the second output branch. The CG-FET in the first output branch and the CS-FET in the second output branch are equal in size such that their transconductances are approximately equal, such that currents in the two output branches are inverted and the outputs at the output nodes of the two output branches are differential outputs.

Abstract: A variable-gain, low noise amplifier system includes a variable-gain, low noise amplifier, having a matching stage, coupled to an input signal with a plurality of different carrier frequencies, that provides complementary output signals containing the plurality of different carrier frequencies. The variable-gain, low noise amplifier also includes a set of carrier gain control stages, coupled to the complementary output signals, wherein each carrier gain control stage provides an independent gain for one carrier frequency of the plurality of different carrier frequencies. The variable-gain, low noise amplifier system also includes a gain controller, coupled to the variable-gain, low noise amplifier that provides gain control signals to determine the independent gain for each carrier gain control stage. A method of operating a variable-gain, low noise amplifier is also provided.

Abstract: A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier.

Abstract: A circuit and method for filtering adjacent channel interferers. One embodiment of an adjacent channel filtering circuit for reducing adjacent channel interference with an in-band signal, includes: (1) a radio frequency (RF) circuit configured to receive and down-convert an RF signal to a baseband signal containing an in-band signal and adjacent channel components, (2) a controlled single pole filter electrically coupled to the RF circuit and configured to reject the adjacent channel components and cause a predetermined attenuation in the in-band signal, (3) a baseband circuit coupled to the controlled single pole filter and configured to condition the baseband signal for conversion to a digital signal, and (4) a digital circuit coupled to the baseband circuit and configured to receive the digital signal and compensate for the predetermined attenuation.

Abstract: A radio frequency (RF) circuit for intra-band and inter-band carrier aggregation includes a receive path configured to receive an input signal. The RF circuit includes a low noise amplifier which has multiple separate input stages and multiple separate output stages. Each input stage has multiple separate input paths, wherein each separate input path is configured to be separately activated and connected to one of the output stages. Each separate output stage is configured to be separately activated and connected to a signal mixer that provides signal demodulation of the input signal employing aggregation of carriers corresponding to intra-band or inter-band signals. Methods of operating the RF circuit for intra-band and inter-band carrier aggregation are also provided.

Abstract: A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal.

Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.

Abstract: A circuit and method for filtering adjacent channel interferers. One embodiment of an adjacent channel filtering circuit for reducing adjacent channel interference with an in-band signal, includes: (1) a radio frequency (RF) circuit configured to receive and down-convert an RF signal to a baseband signal containing an in-band signal and adjacent channel components, (2) a controlled single pole filter electrically coupled to the RF circuit and configured to reject the adjacent channel components and cause a predetermined attenuation in the in-band signal, (3) a baseband circuit coupled to the controlled single pole filter and configured to condition the baseband signal for conversion to a digital signal, and (4) a digital circuit coupled to the baseband circuit and configured to receive the digital signal and compensate for the predetermined attenuation.

Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.