Patents by Inventor Abdul Aziz

Abdul Aziz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200270757
    Abstract: A synthetic methodology for robust, nanostructured films of cobalt oxide over metal evaporated gold or similar material layer of, e.g., 50 nm, directly onto glass or other substrates via aerosol assisted chemical vapor deposition (AACVD). This approach allows film growth rates in the range of, e.g., 0.8 nm/s, using a commercially available precursor, which is ˜10-fold the rate of electrochemical synthetic routes. Thus, 250 nm thick cobalt oxide films may be generated in only 5 minutes of deposition time. The water oxidation reaction for such films may start at ˜0.6 V vs Ag/AgCl with current density of 10 mA/cm2 and is achieved at ˜0.75 V corresponding to an overpotential of 484 mV. This current density is further increased to 60 mA/cm2 at ˜1.5 V (vs Ag/AgCl). Electrochemically active surface area (ECSA) calculations indicate that the synergy between a Au-film, acting as electron sink, and the cobalt oxide film(s), acting as catalytic layer(s), are more pronounced than the surface area effects.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Applicant: King Fahd University of Petroleum and Minerals
    Inventors: Muhammad Ali EHSAN, Md. Abdul AZIZ, Abbas Saeed HAKEEM
  • Publication number: 20200235042
    Abstract: An electronic device, a lead frame, and a method, including providing a lead frame with a Y-shaped feature having branch portions connected to a dam bar in a prospective gap in an equally spaced repeating lead pitch pattern, and a set of first leads extending parallel to one another along a first direction and spaced apart from one another along a second direction in lead locations of the repeating lead pitch pattern, attaching a semiconductor die to a die attach pad of the lead frame, attaching bond wires between bond pads of the semiconductor die, and the first leads, enclosing first portions of the first leads, the die attach pad, and a portion of the semiconductor die in a package structure, and performing a dam bar cut process that cuts through portions of the dam bar between the lead locations of the repeating lead pitch pattern.
    Type: Application
    Filed: January 23, 2019
    Publication date: July 23, 2020
    Applicant: Texas Instruments Incorporated
    Inventors: Anis Fauzi Bin Abdul Aziz, Lee Han Meng@Eugene Lee, Wei Fen Sueann Lim, Siew Kee Lee
  • Patent number: 10720406
    Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: July 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Khoo Yien Sien
  • Publication number: 20200218784
    Abstract: A system for facilitating evaluation of characteristics related to quality associated with a machine design may include a user input device configured to generate a query related to one or more characteristics related to quality associated with a machine design. The system may also include a display device configured display images, and a processor in communication with the user input device and the display device. The processor may be configured to receive a query from the user input device, access data representative of the machine design, and generate image data representative of characteristics related to quality associated with the machine design. The image data may be communicated to the display device to display a machine image including a color-coded representation of at least a portion of a machine and a textual image including textual representations of information related to the machine design.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Applicant: Caterpillar Inc.
    Inventors: Yihong Yang, Amit Kashyap, Abdul Aziz Baig Mirza, Abhishek Ramaswamy, Mihai Sandulescu, Jeffrey Paul Sayre, Cody LeRoy Webster, Scott Antonio Zacek
  • Publication number: 20200218785
    Abstract: A system for evaluating characteristics related to quality associated with a machine design may include a user input device and a display device configured to display images representative of characteristics related to quality. The system may also include a processor in communication with the user input device and the display device. The processor may be configured to receive a query from the user input device related to one or more characteristics related to quality, and access data representative of the machine design. The data may include a data format representative of the machine design and including a plurality of nodes. The processor may be configured to associate the plurality of nodes into a node tree structure including a plurality of node branches and generate image data representative of characteristics related to quality associated with the machine design by processing two or more of the node branches substantially concurrently.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Applicant: Caterpillar Inc.
    Inventors: Yihong Yang, Amit Kashyap, Abdul Aziz Baig Mirza, Abhishek Ramaswamy, Mihai Sandulescu, Jeffrey Paul Sayre, Cody LeRoy Webster, Scott Antonio Zacek
  • Patent number: 10699417
    Abstract: Embodiments of present disclosure discloses system and method for acquisition of optimal images of object in multi-layer sample. Initially, images for FOV of multi-layer sample comprising objects are retrieved. Each of images are captured by varying focal depth of image capturing unit associated with system. Further, objects associated with multi-layer sample in FOV are identified. For identification, cumulative foreground mask of FOV is obtained based on adaptive thresholding performed on foreground image of FOV. Based on contour detection performed on cumulative foreground mask of FOV, object masks, corresponding to objects, is obtained for identifying objects. Further, sharpness of each of images associated with each of object masks is computed. Based on sharpness, optimal images from images for each of objects is selected for acquisition of optimal images of objects in multi-layer sample.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 30, 2020
    Assignee: Sigtuple Technologies Private Limited
    Inventors: Bharath Cheluvaraju, Apurv Anand, Rohit Kumar Pandey, Tathagato Rai Dastidar, Abdul Aziz, Apoorva Jakalannanavar Halappa Manjula
  • Publication number: 20200202321
    Abstract: A computer-implemented method and system for a customer experience resource facility for scheduling a time-based resource on a commerce processing device and accepting an input for a product-based resource, and processing a payment in respect of the time-based resource and the product-based resource using a payment processing facility on the commerce processing device, where the payment processing facility processes payments through the commerce processing device based at least in part on an input received from the customer experience resource facility.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Peter Nitsch, Polly Auyeung, Rahil Abdul Aziz, Ricardo Vazquez, Dima Bart, Fahd Ananta
  • Publication number: 20200176296
    Abstract: Aspects of the present disclosure relate to one or more implementations of a substrate support for a processing chamber. In one implementation, a substrate support includes a body having a center, and a support surface on the body configured to at least partially support a substrate. The substrate support includes a first angled wall that extends upward and radially outward from the support surface, and a first upper surface disposed above the support surface. The substrate support also includes a second angled wall that extends upward and radially outward from the first upper surface, the first upper surface extending between the first angled wall and the second angled wall. The substrate support also includes a second upper surface extending from the second angled wall. The second upper surface is disposed above the first upper surface.
    Type: Application
    Filed: November 7, 2019
    Publication date: June 4, 2020
    Inventors: Abdul Aziz KHAJA, Venkata Sharat Chandra PARIMI, Sarah Michelle BOBEK, Prashant Kumar KULSHRESHTHA, Vinay K. PRABHAKAR
  • Publication number: 20200176365
    Abstract: In a described example, a packaged integrated circuit (IC) includes a lead frame with a lead and with an IC chip mount pad. A portion of the lead adjacent to the IC chip mount pad is mechanically deformed to form a lead lock. An integrated circuit chip is mounted on a first side of the IC chip mount pad; and the integrated circuit chip, the IC chip mount pad, and the portion are covered in molding compound.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 4, 2020
    Inventors: Bin Abdul Aziz Anis Fauzi, Wei Fen Sueann Lim, Lee Han Meng@Eugene Lee
  • Patent number: 10663491
    Abstract: A voltage-current sensor enables more accurate measurement of the voltage, current, and phase of RF power that is delivered to high-temperature processing region. The sensor includes a planar body comprised of a non-organic, electrically insulative material, a measurement opening formed in the planar body, a voltage pickup disposed around the measurement opening, and a current pickup disposed around the measurement opening. Because of the planar configuration and material composition of the sensor, the sensor can be disposed proximate to or in contact with a high-temperature surface of a plasma processing chamber.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: May 26, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zheng John Ye, Jay D. Pinson, II, Juan Carlos Rocha, Abdul Aziz Khaja
  • Publication number: 20200135621
    Abstract: A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed.
    Type: Application
    Filed: July 17, 2019
    Publication date: April 30, 2020
    Inventors: YOU CHYE HOW, ANIS FAUZI BIN ABDUL AZIZ
  • Patent number: 10636630
    Abstract: A processing chamber and a processing method for processing a substrate in the processing chamber with thermal control are described herein. The method includes heating a first substrate using a heater apparatus during a first processing operation. The heater apparatus has a first setpoint during at least a first portion of the first processing operation. The first substrate is disposed on a substrate support surface of an electrostatic chuck in a processing chamber. The method further includes determining a first parameter change corresponding to a resistivity change in the electrostatic chuck, determining a second setpoint for the heater apparatus based on the first parameter change, and controlling the heater apparatus to the second setpoint.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hemant P. Mungekar, Ganesh Balasubramanian, Yoichi Suzuki, Abdul Aziz Khaja
  • Patent number: 10629427
    Abstract: Methods for processing a substrate, such as bevel etch processing, are provided. In one embodiment, a method includes placing a substrate on a cover plate inside of a processing chamber, where the substrate has a center and a bevel edge and contains a dielectric layer thereon, the processing chamber contains a mask disposed above the substrate and an edge ring disposed under the substrate, the edge ring has an annular body, and the cover plate is disposed on a support assembly. The method further includes heating the substrate with a heater attached to the support assembly, raising the edge ring to contact the mask, flowing a process gas containing an etchant along an outer surface of the mask and to the bevel edge, where the process gas is ignited to produce a plasma, and exposing an upper surface of the substrate at the bevel edge to the process gas.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 21, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zonghui Su, Vinay Prabhakar, Abdul Aziz Khaja, Jeongmin Lee
  • Patent number: 10603295
    Abstract: The present disclosure provides compositions and methods for treating subjects at risk for or with sensorineural hearing loss. Such compositions and methods include modulating the epigenetic status of the cell, or rate of protein degradation, to increase expression and/or levels of Atoh1 protein.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: March 31, 2020
    Assignee: Massachusetts Eye and Ear Infirmary
    Inventors: Albert Edge, Judith Kempfle, Dunia Abdul-Aziz
  • Patent number: 10599043
    Abstract: Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: March 24, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hiroyuki Ogiso, Jianhua Zhou, Zonghui Su, Juan Carlos Rocha-Alvarez, Jeongmin Lee, Karthik Thimmavajjula Narasimha, Rick Gilbert, Sang Heon Park, Abdul Aziz Khaja, Vinay Prabhakar
  • Publication number: 20200090340
    Abstract: Embodiments of present disclosure discloses system and method for acquisition of optimal images of object in multi-layer sample. Initially, images for FOV of multi-layer sample comprising objects are retrieved. Each of images are captured by varying focal depth of image capturing unit associated with system. Further, objects associated with multi-layer sample in FOV are identified. For identification, cumulative foreground mask of FOV is obtained based on adaptive thresholding performed on foreground image of FOV. Based on contour detection performed on cumulative foreground mask of FOV, object masks, corresponding to objects, is obtained for identifying objects. Further, sharpness of each of images associated with each of object masks is computed. Based on sharpness, optimal images from images for each of objects is selected for acquisition of optimal images of objects in multi-layer sample.
    Type: Application
    Filed: October 3, 2017
    Publication date: March 19, 2020
    Applicant: SIGTUPLE TECHNOLOGIES PRIVATE LIMITED
    Inventors: Bharath CHELUVARAJU, Apurv ANAND, Rohit PANDEY, Tathagato Rai DASTIDAR, Abdul AZIZ, Apoorva JAKALANNANAVAR HALAPPA MANULA
  • Publication number: 20200091111
    Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.
    Type: Application
    Filed: November 19, 2019
    Publication date: March 19, 2020
    Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Khoo Yien Sien
  • Publication number: 20200058539
    Abstract: Embodiments described herein relate to coating materials with high resistivity for use in processing chambers. To counteract the high charges near the top surface of the thermal conductive support, the top surface of the thermal conductive support can be coated with a high resistivity layer. The high resistivity of the layer reduces the amount of charge at the top surface of the thermally conductive element, greatly reducing or preventing arcing incidents along with reducing electrostatic chucking degradation. The high resistivity layer can also be applied to other chamber components. Embodiments described herein also relate to methods for fabricating a chamber component for use in a processing environment. The component can be fabricated by forming a body of a chamber component, optionally ex-situ seasoning the body, installing the chamber component into a processing chamber, in-situ seasoning the chamber component, and performing a deposition process in the processing chamber.
    Type: Application
    Filed: July 23, 2019
    Publication date: February 20, 2020
    Inventors: Sudha RATHI, Dong Hyung LEE, Abdul Aziz KHAJA, Ganesh BALASUBRAMANIAN, Juan Carlos ROCHA
  • Publication number: 20200056086
    Abstract: A method of recovering a hydrocarbon from a reservoir, whereby an oil recovery formulation containing carboxylic acid functionalized-pyrolyzed date leaf particles is injected into the reservoir, and the hydrocarbon is collected from the reservoir. The carboxylic acid functionalized-pyrolyzed date leaf particles are obtained sequentially from date leaves by cutting the date leaves and drying, pulverizing in the presence of a metal bicarbonate, pyrolyzing at 700 to 1,000° C., and treating the product thus obtained with an acid solution that includes nitric acid to introduce carboxylic acid functional groups.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 20, 2020
    Applicant: King Fahd University of Petroleum and Minerals
    Inventors: Md. Bashirul Haq, Md. Abdul Aziz, Abbas Saeed Hakeem, Dhafer A. Al Shehri
  • Patent number: 10541225
    Abstract: A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng @ Eugene Lee, Wei Fen Sueann Lim, Anis Fauzi Bin Abdul Aziz