Abstract: Disclosed are methods and apparatus for qualifying a photolithographic reticle. A reticle inspection tool is used to acquire images at different imaging configurations from each of the pattern areas of a calibration reticle. A reticle near field is recovered for each of the pattern areas of the calibration reticle based on the acquired images from each pattern area of the calibration reticle. Using the recovered reticle near field for the calibration reticle, a lithography model for simulating wafer images is generated based on the reticle near field. Images are then acquired at different imaging configurations from each of the pattern areas of a test reticle. A reticle near field for the test reticle is then recovered based on the acquired images from the test reticle.

Abstract: Systems and methods for detecting defects on a reticle are provided. The embodiments include generating and/or using a data structure that includes pairs of predetermined segments of a reticle pattern and corresponding near-field data. The near-field data for the predetermined segments may be determined by regression based on actual image(s) of a reticle generated by a detector of a reticle inspection system. Inspecting a reticle may then include separately comparing two or more segments of a pattern included in an inspection area on the reticle to the predetermined segments and assigning near-field data to at least one of the segments based on the predetermined segment to which it is most similar. The assigned near-field data can then be used to simulate an image that would be formed for the reticle by the detector, which can be compared to an actual image generated by the detector for defect detection.

Abstract: Methods and systems for performing measurements of semiconductor structures and materials based on scatterometry measurement data are presented. Scatterometry measurement data is used to generate an image of a material property of a measured structure based on the measured intensities of the detected diffraction orders. In some examples, a value of a parameter of interest is determined directly from the map of the material property of the measurement target. In some other examples, the image is compared to structural characteristics estimated by a geometric, model-based parametric inversion of the same measurement data. Discrepancies are used to update the geometric model of the measured structure and improve measurement performance. This enables a metrology system to converge on an accurate parametric measurement model when there are significant deviations between the actual shape of a manufactured structure subject to model-based measurement and the modeled shape of the structure.

Abstract: Disclosed are methods and apparatus for facilitating an inspection of a sample using an inspection tool. An inspection tool is used to obtain an image or signal from an EUV reticle that specifies an intensity variation across the EUV reticle, and this intensity variation is converted to a CD variation that removes a flare correction CD variation so as to generate a critical dimension uniformity (CDU) map without the flare correction CD variation. This removed flare correction CD variation originates from design data for fabricating the EUV reticle, and such flare correction CD variation is generally designed to compensate for flare differences that are present across a field of view (FOV) of a photolithography tool during a photolithography process. The CDU map is stored in one or more memory devices and/or displayed on a display device, for example, of the inspection tool or a photolithography system.

Abstract: Block-to-block reticle inspection includes acquiring a swath image of a portion of a reticle with a reticle inspection sub-system, identifying a first occurrence of a block in the swatch image and at least a second occurrence of the block in the swath image substantially similar to the first occurrence of the block and determining at least one of a location, one or more geometrical characteristics of the block and a spatial offset between the first occurrence of the block and the at least a second occurrence of the block.

Abstract: Apparatus and methods for inspecting a photolithographic reticle are disclosed. A reticle inspection tool is used at one or more operating modes to obtain images of a plurality of training regions of a reticle, and the training regions are identified as defect-free. Three or more basis training images are derived from the images of the training regions. A classifier is formed based on the three or more basis training images. The inspection system is used at the one or more operating modes to obtain images of a plurality of test regions of a reticle. Three or more basis test images are derived from to the test regions. The classifier is applied to the three or more basis test images to find defects in the test regions.

Abstract: Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.

Abstract: A method and system for performing model-based registration and critical dimension measurement is disclosed. The method includes: utilizing an imaging device to obtain at least one optical image of a measurement site specified for a photomask; retrieving a design of photomask and utilizing a computer model of the imaging device to generate at least one simulated image of the measurement site; adjusting at least one parameter of the computer model to minimize dissimilarities between the simulated images and the optical images, wherein the parameters includes at least a pattern registration parameter or a critical dimension parameter; and reporting the pattern registration parameter or the critical dimension parameter of the computer model when dissimilarities between the simulated images and the optical images are minimized.

Abstract: Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Abstract: Disclosed is test structure for measuring wave-front aberration of an extreme ultraviolet (EUV) inspection system. The test structure includes a substrate formed from a material having substantially no reflectivity for EUV light and a multilayer (ML) stack portion, such as a pillar, formed on the substrate and comprising a plurality of alternating pairs of layers having different refractive indexes so as to reflect EUV light. The pairs have a count equal to or less than 15.

Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

Abstract: The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Abstract: Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions.

Abstract: Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first pattern and remains within narrow a space defined by the first pattern; and removing the first pattern from the substrate. In one embodiment, the first pattern can comprise sacrificial material, which can include, for example, polysilicon material. The deposition can comprise physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, atomic layer deposition or other deposition techniques.

Abstract: Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.

Abstract: The present invention provides a method for calibrating a computational model of a lithography process by calculating a demerit function using an intensity measurement at a location of a wafer; and calibrating the lithography model or a mask making model by determining values of parameters of the computational model using the calculated demerit function. The method may also use a second demerit function that is defined by the sum of squares of differences between a simulated and measured critical dimensions of a feature on the wafer.

Abstract: Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.

Abstract: An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating.