Abstract: A memory system and method for delta writes are provided. In one embodiment, a memory system receives a request to store data in the memory and determines whether the data requested to be stored in the memory is a modified version of data already stored in the memory. If it is, the memory system compares the data requested to be stored in the memory with the data already stored in the memory to identify differences between the data to be stored and the data already stored. The memory system then stores the identified differences in the memory, along with a table that maps the stored identified differences to corresponding locations in the data already stored in the memory. Other embodiments are provided.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for the secondary copy blocks may be used to increase the endurance for those blocks. Before programming the secondary copy, the trim parameters may be adjusted to increase endurance and after programming the secondary copy, the trim parameters may be adjusted back to the default value that is used when programming the primary copy.

Abstract: A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: A data storage device includes a first memory die having memory cells and a first transfer data latch. The data storage device also includes a second memory die having second memory cells and a second transfer data latch. A bus is coupled to the first memory die and the second memory die. The data storage device also includes a controller coupled to the bus. The controller is configured to cause the first transfer data latch and the second transfer data latch to store first data responsive to sending the first data to the first memory die for programming of the first data to a first word line of the first memory cells.

Abstract: A server system with one or more processors and memory sends a verification request, to a client device, to verify that the client device is storing a data block, where the verification request includes verification parameters. In response, the server system obtains from the client device a first verification value for the data block. The server system compares the first verification value with a second verification value for the data block, where the second verification value was previously computed, in accordance with the data block and the verification parameters, and stored by the server system. In accordance with a determination that the first verification value matches the second verification value, the server system confirms that the client device is storing the data block.

Abstract: When the number of bad columns in a memory or plane is less than a threshold number then a first Error Correction Code (ECC) scheme encodes user data in first pages of a first size. If the number of bad columns is greater than the threshold number then a second ECC scheme encodes the user data in second pages of a second size that is smaller than the first size.

Abstract: A non-volatile memory system may include a tracking module that tracks logic values of bits to be stored in memory elements identified as unreliable. A record of the logic values may be generated. During decoding of the data, a log likelihood ratio module may use the record to assign log likelihood ratio values for the decoding.

Abstract: A data storage device includes an encoder and a memory that includes multiple storage elements. The encoder is configured to receive input data and to map at least one input group of bits of the input data to generate output data including at least one output group of bits. Each input group of bits of the at least one input group of bits and each output group of bits of the at least one output group of bits has the same number of bits. Each storage element of the multiple storage elements is configured to be programmed to a voltage state corresponding to an output group of bits of the at least one group of bits associated with the storage element.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.

Abstract: A method of operating a data storage device having a memory includes reading error location data associated with a first region of the memory. The memory includes the first region and a second region. The method also includes generating one or more parameters based on the error location data. The method includes receiving data to be written to the memory and encoding the data to produce a codeword. The method also includes partitioning the codeword based on the one or more parameters to generate a first portion and a second portion. The method further includes performing a write operation to store the first portion at the first region and to store the second portion at the second region.

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

Abstract: A storage module may include a non-volatile memory module and a controller that communicates with the non-volatile memory module using a communications bus. In response to receipt of a host command, the controller may generate one or more sets of context commands for communication of data on the communications bus between the controller and an area of memory. The controller may execute the sets of context commands in a cache sequence. During execution of the context commands in the cache sequence, the controller may determine an opportunity window that occurs after execution of a context command of a prior set and before execution of a context command of a current set, during which the controller may utilize the communications bus.

Abstract: A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided.

Abstract: A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: A non-volatile memory system may include a write task queue that queues write commands and a garbage collection module that analyzes information about pending write commands in the write task queue in order to perform garbage collection. Based on its analysis of the write task queue, the garbage collection module performs discouraging actions to discourage itself from selecting certain blocks in a candidate list to be source blocks for garbage collection. In addition or alternatively, the garbage collection module performs encouraging actions to encourage itself to select blocks storing current valid data associated with a write command as source blocks for garbage collection. Write amplification may be reduced as a result of the discouraging and encouraging actions.