Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.

Abstract: When the number of bad columns in a memory or plane is less than a threshold number then a first Error Correction Code (ECC) scheme encodes user data in first pages of a first size. If the number of bad columns is greater than the threshold number then a second ECC scheme encodes the user data in second pages of a second size that is smaller than the first size.

Abstract: In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. Techniques for dealing with bus collisions between the pulses of different chips are also described.

Abstract: Apparatus and methods implemented therein use an ECC procedure to verify and correct errors in data corresponding to pre-programmed configuration data. Verification and correction is performed in a memory system comprising a non-volatile memory (NVM) and a read only memory (ROM). The NVM comprises a plurality of memory pages. On detecting a power-on reset (POR) command at the memory system, a determination is made whether the memory system has previously received the POR command from a host. When it is determined that the memory system has not previously received the POR command from the host, pre-programmed configuration data is read from the ROM and the memory system is initialized using the pre-programmed configuration data. An error correction code (ECC) is generated for the pre-programmed configuration data and the pre-programmed configuration data including the ECC is store in one of the plurality of pages of the NVM memory.

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

Abstract: A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Abstract: A memory system or flash memory device may include a linking or grouping of blocks that are used for dual writing. In particular, meta-blocks in the memory may be linked in such a way that enables a data transfer to simultaneously occur in two meta-blocks. The dual versions of the programming may be used for error correction. If there is a failure or write error in one of the meta-blocks, then the data from the other meta-block may be used. If there is no failure then the secondary meta-block may be erased.

Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.

Abstract: A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.

Abstract: A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for the secondary copy blocks may be used to increase the endurance for those blocks. Before programming the secondary copy, the trim parameters may be adjusted to increase endurance and after programming the secondary copy, the trim parameters may be adjusted back to the default value that is used when programming the primary copy.

Abstract: A cluster association recognition system and related method are described. The system may identify sequences of data clusters in compilations of cluster journals. The system may generate the compilations by populating the cluster journals with cluster identifications associated with host addresses identified in host read requests. Upon receipt of future read requests, the cluster sequences may be used to identify data sets that are associated with a cluster sequence in order to identify further data sets that a host is likely to request.

Abstract: A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.

Abstract: A method of operating a nonvolatile memory block includes reading data from physical units in the block and determining individual error rates for data from the physical units. The error rate data is stored. This is repeated over multiple iterations and aggregated stored error rates are used to identify bad physical units in the block.

Abstract: A non-volatile memory controller coordinates multiple datapath units along a datapath between a host side and a memory side by unit-to-unit communication, or by a datapath control unit that is in communication with multiple datapath units. Data of a data stream is prioritized so that it passes along the datapath without interruption.

Abstract: Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page.

Abstract: In a block-erasable nonvolatile memory array, blocks are categorized as bad blocks, prime blocks, and sub-prime blocks. Sub-prime blocks are identified from their proximity to bad blocks or from testing. Sub-prime blocks are configured for limited operation (e.g. only storing non-critical data, or data copied elsewhere, or using some additional or enhanced redundancy scheme).

Abstract: A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Abstract: A non-volatile memory system may include a tracking module that tracks logic values of bits to be stored in memory elements identified as unreliable. A record of the logic values may be generated. During decoding of the data, a log likelihood ratio module may use the record to assign log likelihood ratio values for the decoding.

Abstract: Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page.