Abstract: A multi-plane non-volatile memory die includes circuits that receive and apply different parameters to different planes while accessing planes in parallel so that different erase blocks are accessed using individualized parameters. Programming parameters, and read parameters can be modified on a block-by-block basis with modification based on the number of write-erase cycles or other factors.

Abstract: A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.

Abstract: A system handles bad blocks in block-based NAND memory by remapping wordlines that are unusable. Rather than eliminate usage of an entire block, the system may dynamically remap the block to exclude only the unusable wordlines. The partial blocks utilize portions of the memory with good wordlines and the portions of memory with bad wordlines are redirected to one or more replacement blocks.

Abstract: A storage controller is configured to find a last-written page in a block in a memory by sending a command to the memory to read a page of data, receiving at least some of the data from that page, and analyzing the at least some of the data from that page to determine if that page is a written page. In one embodiment, the storage controller instructs the memory to read the page of data using a sense time that is shorter than a sense time used to read a page of data in response to a read request from a host controller. Additionally or alternatively, the amount of the data received by the storage controller can be less than the amount of data received when reading a page of data in response to a read request from a host controller.

Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.

Abstract: A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge.

Abstract: A memory die is provided comprising a non-volatile memory organized in physical pages, a transfer data latch in communication with the non-volatile memory, at least one auxiliary data latch in communication with the transfer data latch, and circuitry. The circuitry is configured to receive a plurality of sense commands, wherein each sense command indicates a physical page in the non-volatile memory to be sensed and a portion of the physical page to be stored in the at least one auxiliary data latch. For each sense command, the circuitry is configured to store data from the physical page sensed by the sense command in the transfer data latch and move data from the portion of the physical page indicated by the sense command to an available location in the at least one auxiliary data latch.

Abstract: Apparatus and methods implemented therein use an ECC procedure to verify and correct errors in data corresponding to pre-programmed configuration data. Verification and correction is performed in a memory system comprising a non-volatile memory (NVM) and a read only memory (ROM). The NVM comprises a plurality of memory pages. On detecting a power-on reset (POR) command at the memory system, a determination is made whether the memory system has previously received the POR command from a host. When it is determined that the memory system has not previously received the POR command from the host, pre-programmed configuration data is read from the ROM and the memory system is initialized using the pre-programmed configuration data. An error correction code (ECC) is generated for the pre-programmed configuration data and the pre-programmed configuration data including the ECC is store in one of the plurality of pages of the NVM memory.

Abstract: A memory system and method for delta writes are provided. In one embodiment, a memory system receives a request to store data in the memory and determines whether the data requested to be stored in the memory is a modified version of data already stored in the memory. If it is, the memory system compares the data requested to be stored in the memory with the data already stored in the memory to identify differences between the data to be stored and the data already stored. The memory system then stores the identified differences in the memory, along with a table that maps the stored identified differences to corresponding locations in the data already stored in the memory. Other embodiments are provided.

Abstract: A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes sending a memory command from the controller to the non-volatile memory. The memory command indicates multiple sense operations to be performed at a single plane of the non-volatile memory.

Abstract: In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before a data set is transmitted from one functional block (such the host interface) to another functional block (such as data encryption or ECC), corresponding CRC is generated and transferred with the data. At the second block, the data set can be checked with the CRC at the second block before it operates on the data. This allows the controller to check for internal transfer errors early, allow for corrupted data to be re-requested, such as from a host when this process is applied to a data write operation. After the second block finishes with the data, a new CRC can then be generated to protect the data on its next internal transfer. This arrangement can particularly useful for functional blocks that transform the data set.

Abstract: A method of operating a data storage device having a memory includes reading error location data associated with a first region of the memory. The memory includes the first region and a second region. The method also includes generating one or more parameters based on the error location data. The method includes receiving data to be written to the memory and encoding the data to produce a codeword. The method also includes partitioning the codeword based on the one or more parameters to generate a first portion and a second portion. The method further includes performing a write operation to store the first portion at the first region and to store the second portion at the second region.

Abstract: A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device. An estimate of elapsed time and temperature conditions may be useful for memory management. An algorithm that periodically identifies one or more sentinel blocks in the memory device and measures the data retention shift in those sentinel blocks can calculate a scalar value that approximates the combined effect of elapsed time and/or temperature conditions.

Abstract: A method of operating a nonvolatile memory block includes reading data from physical units in the block and determining individual error rates for data from the physical units. The error rate data is stored. This is repeated over multiple iterations and aggregated stored error rates are used to identify bad physical units in the block.

Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

Abstract: A storage module may be configured to scramble data before the data is stored in memory. The storage module may scramble the data in accordance with a scrambling scheme that identifies a plurality of scrambling keys to use to scramble the data and a pattern in which to use the scrambling keys. The scrambling scheme may be applied to a plurality of sets of pages of the data, and may be repeated for each of the sets. The scrambling scheme may also be used when descrambling the scrambled data, or a copy of the scrambled data.

Abstract: A storage module and method for on-chip copy gather are provided. In one embodiment, a storage module is provided with a memory comprising a plurality of word lines and a plurality of data latches. The memory copies data from a first word line into a first data latch and copies data from a second word line into a second data latch. The memory then copies only some of the data from the first data latch and only some of the data from the second data latch into a third data latch. After that, the memory copies the data from the third data latch to a third word line. In another embodiment, a storage module is provided comprising a memory and an on-chip copy gather module. Other embodiments are provided.

Abstract: In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.

Abstract: A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge.