Abstract: Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: Embodiments of the present disclosure may provide a switching scheme for tri-level unit elements with ISI mitigation. A tri-level unit element may include a first and second current source and a plurality of switches arranged to form three circuit branches between the first and the second current source. The first circuit branch may include two switches connected in parallel between the first current source and a first output terminal and two switches connected in parallel between the second current source and the first output terminal. The second circuit branch may include two switches connected in parallel between the first current source and a second output terminal and two switches connected in parallel between the second current source and the second output terminal. The third circuit branch may include switches to couple the first current source and the second current source to a dump node.

Abstract: Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal.

Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuits

Abstract: Fault detection techniques for control of sensor systems. A sensor control integrated circuit (“IC”) may include a fault detection system for coupling to the sensor supply lines. The system may detect faults for each of the sensor supply lines. The fault detection system may level shift sensor supply line signals from a first voltage domain to a second voltage domain appropriate for the fault detection system of the controller IC. The fault detection system may level shift source potential voltages from the first voltage domain to the second voltage domain to detect predetermined fault types. The fault detection system may compare the second domain voltages from the sensor supply lines to voltages representing predetermined fault types and may generate fault status indicators based on the comparison.

Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input-terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuits

Abstract: A low-power, low-voltage feedback class AB operational amplifier is disclosed. The minimum supply voltage is one gate-source voltage and two saturation voltages. Currents on the output p-type and n-type transistors are monitored as part of the feedback loop control. Accurate monitoring is achieved by connecting current monitors directly to the corresponding voltage rail. Additional output stages may be selectively connected to the primary output stage to dynamically adjust to changes source conditions. Thus by connecting the appropriate number and type of additional output stages, continuous time adaptive power supply compensation is achieved. Both single ended and differential topologies are described.

Abstract: A system for converting digital signals into analog signals using sigma-delta modulation and includes a signed thermometer encoder for converting a plurality of signed binary data received at the encoder into a plurality of signed thermometer data and a rotational dynamic element matching (DEM) arrangement for receiving the plurality of signed binary data and the plurality of signed thermometer data. The rotational DEM arrangement further includes a first barrel shifter for receiving a positive thermometer data at a cycle, the first barrel shifter having a first pointer indicating a starting position of next positive thermometer data, and a second barrel shifter for receiving a negative thermometer data at a cycle, the second shifter having a second pointer indicating a starting position of next negative thermometer data, wherein the first pointer is circularly shifted as a function of positive binary data and the second pointer is circularly shifted as a function of negative binary data.

Abstract: A system for converting digital signals into analog signals using sigma-delta modulation and includes a signed thermometer encoder for converting a plurality of signed binary data received at the encoder into a plurality of signed thermometer data and a rotational dynamic element matching (DEM) arrangement for receiving the plurality of signed binary data and the plurality of signed thermometer data. The rotational DEM arrangement further includes a first barrel shifter for receiving a positive thermometer data at a cycle, the first barrel shifter having a first pointer indicating a starting position of next positive thermometer data, and a second barrel shifter for receiving a negative thermometer data at a cycle, the second shifter having a second pointer indicating a starting position of next negative thermometer data, wherein the first pointer is circularly shifted as a function of positive binary data and the second pointer is circularly shifted as a function of negative binary data.

Abstract: A low-power, low-voltage feedback class AB operational amplifier is disclosed. The minimum supply voltage is one gate-source voltage and two saturation voltages. Currents on the output p-type and n-type transistors are monitored as part of the feedback loop control. Accurate monitoring is achieved by connecting current monitors directly to the corresponding voltage rail. Additional output stages may be selectively connected to the primary output stage to dynamically adjust to changes source conditions. Thus by connecting the appropriate number and type of additional output stages, continuous time adaptive power supply compensation is achieved. Both single ended and differential topologies are described.

Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input-terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuits

Abstract: In one exemplary embodiment, a programmable analog array (PAA) contains a configurable analog matrix having two floating-gate field effect transistors (FETs). Also contained in the PAA is an interconnect circuit that is programmable to configure the configurable analog matrix to operate in one or more of several matrix modes. A few examples of such matrix modes include a switching matrix mode, a memory matrix mode, and a computing matrix mode. In an exemplary method of configuring the PAA. PAA, the the method includes programming an interconnection, for example, between a first terminal of the first floating-gate FET and a first terminal of the second floating-gate FET. The method further includes programming an interconnection, for example, between a gate terminal of the first floating-gate FET and a fixed voltage source, for setting a floating gate charge on the first floating-gate FET.

Abstract: Systems and methods for configuring a floating-gate transistor device to perform a computational function upon an input signal that is coupled into a floating-gate of the floating gate field-effect transistor, wherein the computational function is dependent upon a charge that is programmed into the floating-gate of the floating-gate field effect transistor. Also provided is a configuration circuit that is used to configure circuit parameters of the floating gate field-effect transistor in order to perform the computational function. In one embodiment, the floating gate transistor, which is a floating-gate pFET, is part of an analog memory array.