Abstract: The present disclosure generally relates to systems, methods, and computer-readable media for managing the generation and processing of charging data records (CDRs) in a telecommunication environment (e.g., a fourth generation (4G) a fifth generation (5G), or future generation mobile network). The systems described herein involve predicting lengths of CDRs prior to encoding and providing the CDRs to a charging gateway function to ensure that the CDRs do not exceed a maximum allowable length that the charging gateway function is capable of processing while also reducing the total number of CDR packages that are encoded and transmitted. Indeed, the systems described herein can predict the length of the CDRs incrementally as charging containers are added, thus limiting the number of CDRs that are generated and processed.

Abstract: An example electronic device includes a display device, and a sensor to detect position data of a user of the electronic device. The position data indicates a position and orientation of the user relative to the display device. In addition, the electronic device includes a controller coupled to the sensor and the display device. The controller is to: receive the position data from the sensor; use a machine learning model and the position data to classify an interaction of the user with the electronic device in a first ergonomic category or a second ergonomic category; and adjust an angular position of a display device or an output from the display device responsive to a classification of the interaction in the first ergonomic category.

Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder circuit. The integrated circuit includes a carry generation circuit configured to receive a first input and a second input to generate a carry, and a carry propagation circuit configured to receive the first input, the second input, and a third input to generate a propagated output. The integrated circuit further includes a carry output generation circuit configured to receive the generated carry and the propagated output to generate a final carry as an output, and a sum generation circuit configured to generate a sum output. The sum generation circuit includes the carry generation circuit and is configured to receive the first input, the second input, and generated carry to generate an exclusive NOR output, and further uses the generated exclusive NOR output and the third input to generate the sum output.

Abstract: Techniques for providing location identifiers of devices to render image data comprising faces are described. According to an example of the present subject matter, a face present in image data is detected. A contact identifier corresponding to the face is obtained and a location identifier of a device to render image data is sent to the contact identifier.

Abstract: Techniques for providing location identifiers of devices to render image data comprising faces are described. According to an example of the present subject matter, a face present in image data is detected. A contact identifier corresponding to the face is obtained and a location identifier of a device to render image data is sent to the contact identifier.

Abstract: An image forming apparatus may include a receiving unit to receive a print request to print a document. Further, the image forming apparatus may include an extraction unit to extract content from the document. Furthermore, the image forming apparatus may include a categorization unit to determine a type of the content by applying a machine learning model to the extracted content. Further, the image forming apparatus may include a controller to manage the print request based on the type of the content.

Abstract: In an example, a non-transitory machine-readable storage medium storing instructions executable by a processor of a computing device to receive device telemetry data associated with an electronic device. The device telemetry data may include data that affects a performance of a graphics processor of the electronic device. Further, instructions may be executed by the processor to predict health of the graphics processor by applying a machine learning model to the device telemetry data. Furthermore, instructions may be executed by the processor to generate an alert notification based on the predicted health of the graphics processor.

Abstract: In an example, a non-transitory machine-readable storage medium storing instructions executable by a processor of a computing device to receive device telemetry data associated with an electronic device. The device telemetry data may include data that affects a performance of a graphics processor of the electronic device. Further, instructions may be executed by the processor to predict health of the graphics processor by applying a machine learning model to the device telemetry data. Furthermore, instructions may be executed by the processor to generate an alert notification based on the predicted health of the graphics processor.

Abstract: Techniques for providing location identifiers of devices to render image data comprising faces are described. According to an example of the present subject matter, a face present in image data is detected. A contact identifier corresponding to the face is obtained and a location identifier of a device to render image data is sent to the contact identifier.

Abstract: A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.

Abstract: In an example, a non-transitory machine-readable storage medium may include instructions that, when executed by a processor of a computing device, cause the processor to receive device usage data associated with an electronic device. Further, instructions may be executed by the processor to determine a touch-related contamination state of a surface of the electronic device by applying a machine learning model to the device usage data. Furthermore, instructions may be executed by the processor to send an alert notification to the electronic device based on the touch-related contamination state.

Abstract: A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

Abstract: In an example in accordance with the present disclosure, a system is described. The system includes a database. The data base includes 1) forecasted values of an event indexed by date and 2) actual values of the event indexed by date. The system also includes a non-transitory machine-readable storage medium to store instructions. The system also includes a processor to execute the instructions. The instructions to cause the processor to determine, from a current date and based on a forecasting frequency and forecasting category for forecasted values, previous dates for which there is both a forecasted value and an actual value. The instructions also cause the processor to identify those previous dates for which there is both an actual value and a forecasted value as dates by which a forecasting model accuracy is to be determined.

Abstract: A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.

Abstract: The disclosed technology is generally directed to a Resource Planning system. In one example of the technology, at a first site, a plurality of messages is received from a second site. The messages of the plurality of messages are associated with events. The events include dependencies that are associated with the events. The first site is not the second site. The events are associated with at least one of updating data or updating perpetual cost calculations. Messages of the plurality of messages having a first dependency level are determined based on the dependencies. The messages determined to have the first dependency level are processed. Messages of the plurality of messages having a second dependency level based on the dependencies are determined. The messages determined to have the second dependency level are processed after processing the messages determined to have the first dependency level.

Abstract: The disclosed technology is generally directed to a Resource Planning system. In one example of the technology, at a first site, a plurality of messages is received from a second site. The messages of the plurality of messages are associated with events. The events include dependencies that are associated with the events. The first site is not the second site. The events are associated with at least one of updating data or updating perpetual cost calculations. Messages of the plurality of messages having a first dependency level are determined based on the dependencies. The messages determined to have the first dependency level are processed. Messages of the plurality of messages having a second dependency level based on the dependencies are determined. The messages determined to have the second dependency level are processed after processing the messages determined to have the first dependency level.

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Abstract: A CMOS transistor circuit including: a first block generating a first output signal of a NOR state, in response to first and second input signals; a second block including a first AND-OR gate, the second block generating a second output signal of an OR or an AND state, the second block receiving the first and second input signals and the first output signal; a third block generating a third output signal of the NOR state, in response to a third input signal and the second output signal; a fourth block including a second AND-OR gate, the fourth block generating a fourth output signal of the OR or the AND state in response to the third input signal, the second output signal and the third output signal; and a fifth block including an inverter gate, the fifth block generating a fifth output signal in response to the fourth output signal.

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.