Abstract: A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.

Abstract: An example electronic computing device can be programmed to: receive a status and a date for each of a plurality of loan components associated with a loan transaction, the loan transaction being purchase or refinance of a loan for a property; use an operating service level associated with each of the plurality of loan components to calculate a projected completion date for each of the plurality of loan components; and project a closing date based upon a longest of the projected completion date. The electronic computing device can calculate the operating service levels using artificial intelligence.

Abstract: In an example, a non-transitory machine-readable storage medium storing instructions executable by a processor of a computing device to receive device usage data of an electronic device. Further, instructions may be executed by the processor to receive sensor data indicative of an internal state of the electronic device. The sensor data may include first data associated with a first characteristic of the internal state and second data associated with a second characteristic of the internal state. Furthermore, instructions may be executed by the processor to determine a deviation associated with a component of the electronic device by applying a machine learning model to the device usage data and the sensor data. The deviation may be associated with the first characteristic, the second characteristic, or both. Further, instructions may be executed by the processor to generate an alert notification based on the deviation.

Abstract: A multibit flip flop is provided. The multibit flip flop includes: a first stage one-bit flip flop; and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal. The first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. The first stage one-bit flip flop is further configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop. The second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.

Abstract: An apparatus includes a circuit including a force amplifier having an output, a resistor having a first terminal coupled to the output of the force amplifier, and a second terminal. The circuit also includes a diode clamp including a first diode having a first terminal coupled to the first terminal of the resistor, and having a second terminal coupled to the second terminal of the resistor, the first diode having a first orientation. The diode clamp also includes a second diode coupled in parallel with the first diode between the first and second terminals of the resistor, the second diode having a second orientation opposite than the first diode.

Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder (FA) circuit. The FA circuit comprises a sum generation circuit configured to generate a sum output and a carry output generation circuit configured to generate a carry output. The sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate. The carry output generation circuit comprises a first or-and-invert (OAI) gate, a second OAI gate, and a NAND gate. The first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of a first operand and a second operand. The second OAI gate is configured to receive the output of the NAND gate, an inverse of a carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output.

Abstract: A device includes one or more processors configured to determine, based on a transmission from a second device, data indicative of estimated acoustic coupling to the second device. The one or more processors are further configured to cause the data and an identifier of a multidevice communication session to be sent to an audio controller. The one or more processors are further configured to receive, from the audio controller, an indicator of audio settings associated with the multidevice communication session.

Abstract: A method of optimizing area of logic cells includes creating a plurality of terminator cells for the logic cell, wherein the logic cell includes a plurality of cells. The plurality of terminator cells are placed at the boundary or edge of the logic cells.

Abstract: An example electronic device includes a display device, and a sensor to detect position data of a user of the electronic device. The position data indicates a position and orientation of the user relative to the display device. In addition, the electronic device includes a controller coupled to the sensor and the display device. The controller is to: receive the position data from the sensor; use a machine learning model and the position data to classify an interaction of the user with the electronic device in a first ergonomic category or a second ergonomic category; and adjust an angular position of a display device or an output from the display device responsive to a classification of the interaction in the first ergonomic category.

Abstract: Provided is an apparatus that includes an integrated circuit including a static complementary metal-oxide-semiconductor based full adder circuit. The integrated circuit includes a carry generation circuit configured to receive a first input and a second input to generate a carry, and a carry propagation circuit configured to receive the first input, the second input, and a third input to generate a propagated output. The integrated circuit further includes a carry output generation circuit configured to receive the generated carry and the propagated output to generate a final carry as an output, and a sum generation circuit configured to generate a sum output. The sum generation circuit includes the carry generation circuit and is configured to receive the first input, the second input, and generated carry to generate an exclusive NOR output, and further uses the generated exclusive NOR output and the third input to generate the sum output.

Abstract: Techniques for providing location identifiers of devices to render image data comprising faces are described. According to an example of the present subject matter, a face present in image data is detected. A contact identifier corresponding to the face is obtained and a location identifier of a device to render image data is sent to the contact identifier.

Abstract: Techniques for providing location identifiers of devices to render image data comprising faces are described. According to an example of the present subject matter, a face present in image data is detected. A contact identifier corresponding to the face is obtained and a location identifier of a device to render image data is sent to the contact identifier.

Abstract: An image forming apparatus may include a receiving unit to receive a print request to print a document. Further, the image forming apparatus may include an extraction unit to extract content from the document. Furthermore, the image forming apparatus may include a categorization unit to determine a type of the content by applying a machine learning model to the extracted content. Further, the image forming apparatus may include a controller to manage the print request based on the type of the content.

Abstract: In an example, a non-transitory machine-readable storage medium storing instructions executable by a processor of a computing device to receive device telemetry data associated with an electronic device. The device telemetry data may include data that affects a performance of a graphics processor of the electronic device. Further, instructions may be executed by the processor to predict health of the graphics processor by applying a machine learning model to the device telemetry data. Furthermore, instructions may be executed by the processor to generate an alert notification based on the predicted health of the graphics processor.

Abstract: In an example, a non-transitory machine-readable storage medium storing instructions executable by a processor of a computing device to receive device telemetry data associated with an electronic device. The device telemetry data may include data that affects a performance of a graphics processor of the electronic device. Further, instructions may be executed by the processor to predict health of the graphics processor by applying a machine learning model to the device telemetry data. Furthermore, instructions may be executed by the processor to generate an alert notification based on the predicted health of the graphics processor.

Abstract: Techniques for providing location identifiers of devices to render image data comprising faces are described. According to an example of the present subject matter, a face present in image data is detected. A contact identifier corresponding to the face is obtained and a location identifier of a device to render image data is sent to the contact identifier.

Abstract: A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.

Abstract: In an example, a non-transitory machine-readable storage medium may include instructions that, when executed by a processor of a computing device, cause the processor to receive device usage data associated with an electronic device. Further, instructions may be executed by the processor to determine a touch-related contamination state of a surface of the electronic device by applying a machine learning model to the device usage data. Furthermore, instructions may be executed by the processor to send an alert notification to the electronic device based on the touch-related contamination state.

Abstract: A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.