Abstract: A method and a sense amplifier flip-flop (SAFF) for fixing setup time violations in an integrated circuit (IC) design. The SAFF includes a master latch coupled to a slave latch, wherein the master latch includes a sense amplifier and the SAFF is configured with an equal number of p-type metal oxide semiconductor (PMOS) transistors and n-type metal oxide semiconductor (NMOS) transistors to reduce block area of an integrated circuit (IC). The method includes receiving a clock signal, receiving a data signal, applying the data signal to the sense amplifier when the clock signal is at a low level, wherein a portion of the sense amplifier is responsive to the inverted clock signal, storing a value of the data signal in the slave latch when the clock signal transitions from the low level to the high level, and providing an output signal from the slave latch.

Abstract: A D flip-flop includes a master block configured to latch an input value of D at one of rising edge and a falling edge of a clock signal, based on the clock signal, the input value of D, and an inverted value of D, and a slave block configured to propagate the input value of D at another one of the falling edge and the rising edge of the clock signal, based on the clock signal.

Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

Abstract: An analog-to-digital convertor circuit converts the output of a loop filter circuit to a digital signal. A random sequence generation circuit generates a random sequence. Adder circuitry adds the random sequence to the digital signal to generate a randomized digital signal. Noise transfer function impulse response detection circuitry processes the randomized digital signal and the random sequence to determine a noise transfer function impulse response. Loop filter configuration circuitry configures the loop filter circuit based on the noise transfer function impulse response. The random sequence generation circuit may comprises a high-pass sigma delta modulator. The noise transfer function impulse response detection circuitry may determine the noise transfer function impulse response, and the loop filter configuration circuitry may configure the loop filter based on the noise transfer function impulse response.

Abstract: An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Abstract: A system is configured to perform operations that include receiving an input corresponding to a transaction by a user at a merchant location and determining, based on the input, an identifier corresponding to the user. The operations also include authenticating, via an electronic network, the user with a payment provider server of a payment provider and accessing from the payment provider server based on the identifier, digital wallet information corresponding an account of the user that is maintained by the payment provider. The operations further include receiving a selection of a first digital payment instrument of one or more digital payment instruments and transmitting, via a payment network to a payment processor, payment instructions that cause the payment processor to process a payment corresponding to the transaction using first payment information associated with the first digital payment instrument.

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Abstract: Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Abstract: A computing module that calls to another computing module is run. An isolation context is detected in the module, and all original method calls that are to be detoured are replaced with detouring method calls. The module, with the detouring method calls, is run. When a context change is detected, the module is reset with the original method calls.

Abstract: A system for reconciling physical items in a facility is provided. The system includes a data store containing item information relative to items stored within the facility. A processor is coupled to the data store and is configured to perform at least one control function relative to the items. A user interface component is coupled to the processor and is configured to receive information defining a cycle count relative to at least some items stored within the facility. A network component is coupled to the processor and is configured to convey container information to a plurality of terminals based on the defined cycle count. A virtual count engine is configured to receive observation data from the plurality of terminals associated with the container information. The virtual count engine is configured to group the observation data according to item identifiers and compare the grouped information with information maintained in the data store.