Patents by Inventor Abhishek Sharma

Abhishek Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240061662
    Abstract: Technologies related to constructing a data flow graph are described herein, where the data flow graph indicates that personal data is passed from a first computer-executable module of an organization computing system to a second computer-executable module of the organization computing system. The data flow graph is constructed based upon static analysis data pertaining to source code of the organization computing system; the data flow graph is further constructed based upon infrastructure data that provides runtime information for the organization computing system.
    Type: Application
    Filed: September 21, 2021
    Publication date: February 22, 2024
    Inventors: Leila Rose Golchehreh, Abhishek Sharma
  • Publication number: 20240064958
    Abstract: Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: Aaron LILAK, Sean T. MA, Abhishek SHARMA
  • Publication number: 20240064624
    Abstract: A network operating system receives a bundle file transmitted from a vendor terminal of a vendor providing a network service, the bundle file including first data defining a functional unit group that achieves the network service and second data defining a monitoring policy for the network service. The NOS constructs the functional unit group based on the first data of the bundle file when the network service is purchased by a purchaser. The NOS executes a monitoring process on the functional unit group based on information on the functional unit group to be constructed and the second data of the bundle file.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Shinya KITA, Puneet DEVADIGA, Rajat SINGH, Bharath RATHINAM, Abhishek SHARMA, Rahul ATRI
  • Publication number: 20240061951
    Abstract: A method and a system for managing healthcare records of a user are provided. The method includes storing an electronic medical record related to the user in form of a non-fungible token (NFT) written to a blockchain, associating a smart contract to the NFT in the blockchain, authorizing a request to access the electronic medical record related to the user based on the defined ownership of the electronic medical record stored in the blockchain, identifying one or more NFTs from the blockchain comprising one or more electronic medical records related to the user based on processing of the identifier information in associated one or more smart contracts therewith, in response to the request, and sending the one or more electronic medical records corresponding to the identified one or more NFTs to a requestor associated with the request.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Shanghai United Imaging Intelligence Co., LTD.
    Inventors: Arun Innanje, Abhishek Sharma, Benjamin Planche, Meng Zheng, Shanhui Sun, Ziyan Wu, Terrence Chen
  • Publication number: 20240050006
    Abstract: The system comprises a prediction module (1) equipped with artificial intelligence to predict neurological disorders in an individual patient and identify a level of neurological disorders; a central processing unit (2) to detect triggering events and circumstances due to which the neurological disorders trigger in an individual patient upon receiving real-time behavior information data generated by a playing ball (3) of an individual patient and distinguish between a normal behavior and a neurological disorders behavior; an alert module (4) to alert the individual patient upon determining neurological disorders behavior; and an entertainment platform (5) to entertain and engage the individual patient with a specific set of activities assigned according to detected triggering events and circumstances upon determining the neurological disorders behavior, wherein a specific set of activities includes listening to music, playing games, and talking to an AI chatbot.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 15, 2024
    Inventors: Abhishek Sharma, Ahmed I. Alutaibi, Mohammed Alshehri, Sunil Kumar Sharma, Prateek Jain, Vikas Bajpai
  • Publication number: 20240055531
    Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Jack T. Kavalieros, Shriram Shivaraman, Benjamin Chu-Kung, Yih Wang, Tahir Ghani
  • Publication number: 20240051523
    Abstract: A computer includes a processor and a memory, the memory storing instructions executable by the processor to receive sensor data indicating an obstacle, formulate a control barrier function for a vehicle based on the sensor data, determine a control input based on the control barrier function, and actuate a component of the vehicle according to the control input. The control barrier function is defined with respect to a reference point that is spaced from a centroid of the vehicle.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Applicant: Ford Global Technologies, LLC
    Inventors: Mohit Srinivasan, Hongtei Eric Tseng, Michael Hafner, Mrdjan J. Jankovic, Abhishek Sharma, Erol Dogan Sumer, Alexander Jaeckel, Aakar Mehra
  • Patent number: 11896408
    Abstract: Automated patient positioning and modelling includes a hardware processor to obtain image data from an imaging sensor, classify the image data, using a first machine learning model, as a patient pose based on one or more pre-defined protocols for patient positioning, provide a confidence score based on the classification of the image data and if the confidence score is less than a pre-determined value, re-classify the image data using a second machine learning model; or if the confidence score is greater than a pre-determined value, identify the image data as corresponding to a patient pose based on one or more pre-defined protocols for patient positioning during a scan procedure.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 13, 2024
    Assignee: Shanghai United Imaging Intelligence Co., LTD.
    Inventors: Meng Zheng, Abhishek Sharma, Srikrishna Karanam, Ziyan Wu
  • Patent number: 11901404
    Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Sudipto Naskar, Manish Chandhok, Abhishek A. Sharma, Roman Caudillo, Scott B. Clendenning, Cheyun Lin
  • Publication number: 20240049450
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Jared STOEGER, Yu-Wen HUANG, Shu ZHOU
  • Publication number: 20240046536
    Abstract: The embodiments herein provide a system and method for personalized cartoon image generation. The method (100) comprises launching a keyboard interface (101), capturing a digital picture (102), face segmentation using neural network (103), normalization of segmented face (104), face cartoonification (105), which generates bobble head, facial landmark extraction (106), facial expression feature transfer (109) and customization of the generated plurality of cartoon images (110). Hence, the embodiments herein helps in creation of personalized plurality of cartoon images to make the user part of the conversations and the graphics or content shared look similar to the user input face and more aesthetically pleasing instead of using any reference stickers to convey the messages.
    Type: Application
    Filed: November 11, 2022
    Publication date: February 8, 2024
    Inventors: Rahul Prasad, ABHISHEK SHARMA, MUDIT RASTOGI
  • Patent number: 11895824
    Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Gilbert Dewey, Abhishek A Sharma
  • Patent number: 11895846
    Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Patent number: 11888034
    Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: January 30, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ashish Agarwal, Urusa Alaan, Christopher Jezewski, Kevin Lin, Carl Naylor
  • Publication number: 20240030213
    Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 25, 2024
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Abhishek A. Sharma, Mauro J. Kobrinsky, Doug B. Ingerly
  • Patent number: 11881517
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: January 23, 2024
    Inventors: Abhishek Sharma, Cory Weber, Van H. Le, Sean Ma
  • Patent number: 11880567
    Abstract: A request to perform a storage operation for a storage system is received. It is determined that the requested storage operation is associated with a policy that requires a quorum of approvals before being allowed to be performed. It is determined whether the quorum of approvals has been obtained. In response to a determination that the quorum of approvals has been obtained, a command to perform the requested operation is provided to the storage system.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: January 23, 2024
    Assignee: Cohesity, Inc.
    Inventors: Harsha Vardhan Jagannati, Abhishek Sharma
  • Publication number: 20240008255
    Abstract: Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.
    Type: Application
    Filed: May 30, 2023
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Tahir Ghani, Anand S. Murthy, Cory E. Weber, Rishabh Mehandru, Wilfred Gomes, Pushkar Sharad Ranade
  • Publication number: 20240006395
    Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Sagar Suthram, Debendra Mallik, Wilfred Gomes, Pushkar Sharad Ranade, Nitin A. Deshpande, Omkar G. Karhade, Ravindranath Vithal Mahajan, Abhishek A. Sharma
  • Publication number: 20240008259
    Abstract: Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Tahir Ghani, Anand Murthy, Wilfred Gomes, Sagar Suthram