Patents by Inventor Abhishek Sharma
Abhishek Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11031072Abstract: Described herein are apparatuses, systems, and methods associated with a memory circuit that includes memory cells having respective threshold switches. The memory cells may include a selector transistor with a gate terminal coupled to a word line to receive a word line signal, a drain terminal coupled to a bit line to receive a bit line signal, and a source terminal coupled to a first terminal of the threshold switch. The threshold switch may switch from a high resistance state to a low resistance state when a voltage across the first terminal and a second terminal exceeds a threshold voltage and may remain in the low resistance state after switching when the voltage across the first and second terminals is equal to or greater than a holding voltage that is less than the threshold voltage. Other embodiments may be described and claimed.Type: GrantFiled: September 28, 2017Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Abhishek A. Sharma, Ravi Pillarisetty, Brian S. Doyle, Prashant Majhi
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Patent number: 11031503Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.Type: GrantFiled: September 27, 2016Date of Patent: June 8, 2021Assignee: Intel CorporationInventors: Abhishek A. Sharma, Van H. Le, Gilbert Dewey, Rafael Rios, Jack T. Kavalieros, Yih Wang, Shriram Shivaraman
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Publication number: 20210166691Abstract: Modifying operation of an intelligent agent in response to facial expressions and/or emotions.Type: ApplicationFiled: December 23, 2020Publication date: June 3, 2021Inventors: Siddharth Khullar, Abhishek Sharma, Jerremy Holland, Nicholas E. Apostoloff, Russell Y. Webb, Tai-Peng Tian, Tomas J. Pfister
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Publication number: 20210158167Abstract: Methods and systems for enhancing a distributed medical network. For example, a computer-implemented method includes inputting training data corresponding to each local computer into their corresponding machine learning model; generating a plurality of local losses including generating a local loss for each machine learning model based at least in part on the corresponding training data; generating a plurality of local parameter gradients including generating a local parameter gradient for each machine learning model based at least in part on the corresponding local loss; generating a global parameter update based at least in part on the plurality of local parameter gradients; and updating each machine learning model hosted at each local computer of the plurality of local computers by at least updating their corresponding active parameter set based at least in part on the global parameter update.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: ABHISHEK SHARMA, ARUN INNANJE, ZIYAN WU, SHANHUI SUN, TERRENCE CHEN
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Publication number: 20210158937Abstract: A medical system may utilize a modular and extensible sensing device to derive a two-dimensional (2D) or three-dimensional (3D) human model for a patient in real-time based on images of the patient captured by a sensor such as a digital camera. The 2D or 3D human model may be visually presented on one or more devices of the medical system and used to facilitate a healthcare service provided to the patient. In examples, the 2D or 3D human model may be used to improve the speed, accuracy and consistency of patient positioning for a medical procedure. In examples, the 2D or 3D human model may be used to enable unified analysis of the patient's medical conditions by linking different scan images of the patient through the 2D or 3D human model. In examples, the 2D or 3D human model may be used to facilitate surgical navigation, patient monitoring, process automation, and/or the like.Type: ApplicationFiled: April 28, 2020Publication date: May 27, 2021Applicant: SHANGHAI UNITED IMAGING INTELLIGENCE CO., LTD.Inventors: Ziyan Wu, Srikrishna Karanam, Arun Innanje, Shanhui Sun, Abhishek Sharma, Yimo Guo, Zhang Chen
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Patent number: 11017843Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.Type: GrantFiled: June 28, 2019Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Abhishek Sharma, Gilbert Dewey, Willy Rachmady, Van Le, Matthew Metz, Jack Kavalieros
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Patent number: 11016701Abstract: Techniques and mechanisms for a memory device to perform in-memory computing based on a logic state which is detected with a voltage-controlled oscillator (VCO). In an embodiment, a VCO circuit of the memory device receives from a memory array a first signal indicating a logic state that is based on one or more currently stored data bits. The VCO provides a conversion from the logic state being indicated by a voltage characteristic of the first signal to the logic state being indicated by a corresponding frequency characteristic of a cyclical signal. Based on the frequency characteristic, the logic state is identified and communicated for use in an in-memory computation at the memory device. In another embodiment, a result of the in-memory computation is written back to the memory array.Type: GrantFiled: September 28, 2018Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Ian Young, Ram Krishnamurthy, Sasikanth Manipatruni, Amrita Mathuriya, Abhishek Sharma, Raghavan Kumar, Phil Knag, Huseyin Sumbul, Gregory Chen
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Patent number: 11019263Abstract: Systems and methods may provide for capturing 360 degree video, and multi-resolution encoding, processing and displaying of the video based on a field of view (FOV) and region of interest (ROI) for a viewer. The ROI may be determined based on eye tracking information (ETI) and the video may be encoded for viewports within the FOV at a high resolution and for other viewports outside the FOV at a lower resolution. ROI in the video may be encoded at a high resolution and areas outside of the ROI may be encoded at a lower resolution. The ETI enables the selective display of one or more warnings based on the gaze of a user to improve the efficiency of the warning. 3D glasses having variable lens may be used to adjust the focal distance of a virtual display to match a virtual distance of an object based on stereo distance cues.Type: GrantFiled: April 13, 2020Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Stanley J. Baran, Abhishek R. Appu, Sang-Hee Lee, Atthar H. Mohammed, Jong Dae Oh, Hiu-Fai R. Chan, Joydeep Ray, Barnan Das, Archie Sharma, Richmond Hicks, Changliang Wang, Satyanarayana Avadhanam, Robert J. Johnston, Narayan Biswal
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Patent number: 11018075Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.Type: GrantFiled: December 17, 2018Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
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Publication number: 20210151438Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.Type: ApplicationFiled: November 20, 2019Publication date: May 20, 2021Applicant: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
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Publication number: 20210150330Abstract: A system comprising a first computing apparatus in communication with multiple second computing apparatuses. The first computing apparatus may obtain a plurality of first trained machine learning models for a task from the multiple second computing apparatuses. At least a portion of parameter values of the plurality of first trained machine learning models may be different from each other. The first computing apparatus may also obtain a plurality of training samples. The first computing apparatus may further determine, based on the plurality of training samples, a second trained machine learning model by learning from the plurality of first trained machine learning models.Type: ApplicationFiled: November 18, 2019Publication date: May 20, 2021Applicant: SHANGHAI UNITED IMAGING INTELLIGENCE CO., LTD.Inventors: Abhishek SHARMA, Arun INNANJE, Ziyan WU, Shanhui SUN, Terrence CHEN
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Patent number: 11009957Abstract: A system includes a computer programmed to identify a plurality of audio amplitudes of an audio input. The computer is programmed to identify a plurality of time intervals of the audio input between respective identified audio amplitudes. The computer is programmed to map a haptic pattern based on identified audio amplitudes and the time intervals. The computer is programmed to actuate a motor to output the haptic pattern.Type: GrantFiled: June 27, 2017Date of Patent: May 18, 2021Assignee: Ford Global Technologies, LLCInventors: Yifan Chen, Abhishek Sharma, Qianyi Wang, Steven Lin
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Patent number: 11011550Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.Type: GrantFiled: December 28, 2016Date of Patent: May 18, 2021Assignee: Intel CorporationInventors: Van Le, Abhishek Sharma, Gilbert Dewey, Ravi Pillarisetty, Shriram Shivaraman, Tahir Ghani, Jack Kavalieros
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Publication number: 20210142912Abstract: Systems and methods disclosed provide ways for Health Care Professionals (HCPs) to be involved in initial patient system set up so that the data received is truly transformative, such that the patient not just understands what all the various numbers mean but also how the data can be used. For example, in one implementation, a CGM device is configured for use by a HCP, and includes a housing and a circuit configured to receive a signal from a transmitter coupled to an indwelling glucose sensor. A calibration module converts the received signal into clinical units. A user interface is provided that is configured to display a measured glucose concentration in the clinical units. The user interface is further configured to receive input data about a patient level, where the input data about the patient level causes the device to operate in a mode appropriate to the patient level.Type: ApplicationFiled: January 7, 2021Publication date: May 13, 2021Inventors: Scott M. Belliveau, Naresh C. Bhavaraju, Darin Edward Chum Dew, Eric Cohen, Anna Leigh Davis, Mark Dervaes, Laura J. Dunn, Minda McDorman Grucela, Hari Hampapuram, Matthew Lawrence Johnson, Apurv Ullas Kamath, Steven David King, Katherine Yerre Koehler, Aditya Sagar Mandapaka, Zebediah L. McDaniel, Sumitaka Mikami, Subrai Girish Pai, Philip Mansiel Pellouchoud, Stephen Alan Reichert, Eli Reihman, Peter C. Simpson, Brian Christopher Smith, Stephen J. Vanslyke, Robert Patrick Van Tassel, Matthew D. Wightlin, Richard C. Yang, James Stephen Amidei, David Derenzy, Benjamin Elrod West, Vincent Crabtree, Michael Levozier Moore, Douglas William Burnette, Alexandra Elena Constantin, Nicholas Polytaridis, Dana Charles Cambra, Abhishek Sharma, Kho Braun, Patrick Wile McBride
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Patent number: 11004982Abstract: Substrates, assemblies, and techniques for an apparatus, where the apparatus includes a gate, where the gate includes a first gate side and a second gate side opposite to the first gate side, a gate dielectric on the gate, where the gate dielectric includes a first gate dielectric side and a second gate dielectric side opposite to the first gate dielectric side, a first dielectric, where the first dielectric abuts the first gate side, the first gate dielectric side, the second gate side, and the second gate dielectric side, a channel, where the gate dielectric is between the channel and the gate, a source coupled with the channel, and a drain coupled with the channel, where the first dielectric abuts the source and the drain. In an example, the first dielectric and the gate dielectric help insulate the gate from the channel, the source, and the drain.Type: GrantFiled: March 31, 2017Date of Patent: May 11, 2021Assignee: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Ravi Pillarisetty, Gilbert W. Dewey, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Tahir Ghani
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Publication number: 20210134802Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Applicant: Intel CorporationInventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Tahir Ghani, Doug Ingerly, Rajesh Kumar
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Publication number: 20210130320Abstract: A genus of proteolysis-targeting chimeras (PROTACs)-type compounds/antiestrogens has now been found that act as selective estrogen receptor degraders (SERDs) and estrogen receptor antagonists by degrading and antagonizing ERa in breast cancer cells. The compounds are of the following genus: The compounds described herein exhibit anti-proliferative effects, and are potentially useful, alone or in combination with other therapies, for the treatment of breast cancer. In general, these compounds combine a tight binding ERa targeting ligand tethered to a recognition motif or degron. Once bound, the degron recruits destructive cellular components and the targeted receptor (i.e., ERa) is degraded (i.e., destroyed) or antagonized.Type: ApplicationFiled: June 11, 2019Publication date: May 6, 2021Applicants: STEVENS INSTITUTE OF TECHNOLOGY, MEMORIAL SLOAN-KETTERING CANCER CENTER, THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOISInventors: Abhishek SHARMA, Sarat CHANDARLAPATY, Lucia WANG, Shengjia LIN, Weiyi TOY, John KATZENELLENBOGEN
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Patent number: 10996709Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.Type: GrantFiled: August 30, 2019Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Gururaj Shamanna, Mitesh Goyal, Jagadeesh Chandra Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu
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Patent number: 10996972Abstract: A virtual network interface controller (NIC) associated with a virtual machine in a cloud computing network is configured to support one or more network containers that encapsulate networking configuration data and policies that are applicable to a specific discrete computing workload to thereby enable the virtual machine to simultaneously belong to multiple virtual networks using the single NIC. The network containers supported by the NIC can be associated with a single tenant to enable additional flexibility such quickly switching between virtual networks and support pre-provisioning of additional computing resources with associated networking policies for rapid deployment. The network containers can also be respectively associated with different tenants so that the single NIC can support multi-tenant services on the same virtual machine.Type: GrantFiled: September 25, 2018Date of Patent: May 4, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Abhishek Shukla, Abhishek Ellore Sreenath, Neha Aggarwal, Naveen Prabhat, Nisheeth Srivastava, Xinyan Zan, Ashish Bhargava, Parag Sharma, Rishabh Tewari
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Patent number: 10999244Abstract: The techniques described herein enable a private connectivity solution between a virtual network of a service consumer and a virtual network of a service provider in a cloud-based platform. The techniques map a service (e.g., one or more workloads or containers) executing in the virtual network of the service provider into the virtual network of the service consumer. The mapping uses network address translation (NAT) that is performed by the cloud-based infrastructure. As a result of the techniques described herein, a public Internet Protocol (IP) address does not need to be used to establish a connection thereby alleviating privacy and/or security concerns for the virtual networks of the service provider and/or the service consumer that are hosted by the cloud-based platform.Type: GrantFiled: January 30, 2019Date of Patent: May 4, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Sumeet Mittal, Abhishek Shukla, Rishabh Tewari, Qiming Chen, Harish Kumar Chandrappa, Pranjal Shrivastava, Anitha Adusumilli, Parag Sharma, Abhishek Ellore Sreenath
