Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: Methods, apparatus, and processor-readable storage media for resource forecasting using artificial intelligence techniques are provided herein.

Abstract: Methods, apparatus, and processor-readable storage media for dynamic action classification using machine learning techniques are provided herein. An example computer-implemented method includes generating at least one resource-related forecast by processing, using at least one regression model, resource-related data within at least one predetermined temporal period; converting at least a portion of the at least one resource-related forecast to at least one resource-related action forecast using one or more machine learning techniques in conjunction with one or more temporal lag values; classifying at least one resource-related action associated with at least a portion of the at least one predetermined temporal period by processing at least a portion of the at least one resource-related action forecast using at least one classification model; and performing one or more automated actions based at least in part on the at least one classified resource-related action.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Abstract: Detecting motions associated with a body part of a patient may include using an image sensor installed inside a medical scanner to capture first and second images of the patient inside the medical scanner, wherein the first image may depict the patient in a first state and the second image may depict the patient in a second state. A first area, in the first image, that corresponds to the body part of the patient may be identified and a second area, in the second image, that corresponds to the body part may also be identified so that a first plurality of features may be extracted from the first area of the first image and a second plurality of features may be extracted from the second area of the second image. A motion associated with the body part of the patient may be determined based on the first and second pluralities of features.

Abstract: A method for monitoring operation or status of an electrical submersible pump (ESP) is provided, which includes a) collecting historical time-series data related to ESP operation: b) extracting historical time-series data related to healthy ESP operation from the historical time-series data of a): c) extracting feature data from the historical time-series data extracted in b); d) extracting or calculating values of at least one key performance indicator (KPI) related to healthy ESP operation from the historical times-series data extracted in b): c) using the feature data of c) and the values of at least one KPI of d) to train a machine learning (ML) model to predict at least one target KPI related to healthy ESP operation given feature data as input; and f) using the ML model trained in c) to monitor operation or status of the ESP. Other aspects are described and claimed.

Abstract: A medical system may utilize a modular and extensible sensing device to derive a two-dimensional (2D) or three-dimensional (3D) human model for a patient in real-time based on images of the patient captured by a sensor such as a digital camera. The 2D or 3D human model may be visually presented on one or more devices of the medical system and used to facilitate a healthcare service provided to the patient. In examples, the 2D or 3D human model may be used to improve the speed, accuracy and consistency of patient positioning for a medical procedure. In examples, the 2D or 3D human model may be used to enable unified analysis of the patient's medical conditions by linking different scan images of the patient through the 2D or 3D human model. In examples, the 2D or 3D human model may be used to facilitate surgical navigation, patient monitoring, process automation, and/or the like.

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

Abstract: Thin film transistors having double gates are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate stack is on the insulator layer. A polycrystalline channel material layer is on the first gate stack. A second gate stack is on a first portion of the polycrystalline channel material layer, the second gate stack having a first side opposite a second side. A first conductive contact is adjacent the first side of the second gate stack, the first conductive contact on a second portion of the channel material layer. A second conductive contact is adjacent the second side of the second gate stack, the second conductive contact on a third portion of the channel material layer.

Abstract: An application programming interface (API) call is received to obtain an access data object that includes a permission of an application provider to access a resource of an entity. A previous permission to access a second resource of the entity is identified. As a result of receiving the API call, an access data object is generated to include the permission and the previous permission.

Abstract: An object or person in a medical environment may be identified based on images of the medical environment. The identification may include determining an identifier associated with the object or the person, a position of the object or the person in the medical environment, and a three-dimensional (3D) shape/pose of the object or the person. Representation information that indicates at least the determined identifier, position in the medical environment, and 3D shape/pose of the object or the person may be generated and then used (e.g., by a visualization device) together with one or more predetermined 3D models to determine a 3D model for the object or the person identified in the medical environment and generate a visual depiction of at least the object or the person in the medical environment based on the determined 3D model and the position of the object or the person in the medical environment.

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: Automatic hand gesture determination may be a challenging task considering the complex anatomy and high dimensionality of the human hand. Disclosed herein are systems, methods, and instrumentalities associated with recognizing a hand gesture in spite of the challenges. An apparatus in accordance with embodiments of the present disclosure may use machine learning based techniques to identify the area of an image that may contain a hand and to determine an orientation of the hand relative to a pre-defined direction. The apparatus may then adjust the area of the image containing the hand to align the orientation of the hand with the pre-defined direction and/or to scale the image area to a pre-defined size. Based on the adjusted image area, the apparatus may detect a plurality of hand landmarks and predict a gesture indicated by the hand based on the plurality of detected landmarks.

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.

Abstract: Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More particularly, systems, apparatuses and methods may provide a way to normalize environment information captured by multiple capture devices, and calculate, for an observer, the sound sources or sensed events vector paths. The systems, apparatuses and methods may detect and/or manage one or more capture devices and assign one or more the capture devices based on one or more conditions to provide observer an immersive VR/AR experience.

Abstract: Systems, computer program products, and methods are described herein for auto-scaling volatile memory allocation in an electronic network. The present invention is configured to access metadata of at least one volatile memory component, wherein the metadata is associated with at least one application; determine a current volatile memory allocation for the metadata; determine a current metadata format of the metadata; apply the metadata to a volatile memory allocation machine learning model; generate, based on the application of the metadata to the volatile memory allocation machine learning model, a new volatile memory allocation for the metadata; and apply the new volatile memory allocation to the metadata of the at least one volatile memory component, wherein the application of the new volatile memory allocation to the metadata comprises at least one of an upscaling, a downscaling, or a constant.