Abstract: Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memory are disclosed. An example IC device includes a floating body memory cell comprising a transistor having a first source or drain (S/D) region, a second S/D region, and a gate over a channel portion between the first and second S/D regions; a BL coupled to the first S/D region and parallel to a first axis of a Cartesian coordinate system; a SL coupled to the second S/D region and parallel to a second axis of the coordinate system; and a WL coupled to or being a part of the gate and parallel to a third axis of the coordinate system. IC devices implementing 3D floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced CMOS processes.

Abstract: Thin-film transistors and MIM capacitors in exclusion zones are described. In an example, an integrated circuit structure includes a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors. A back-end-of-line (BEOL) structure is above the semiconductor substrate. A thin-film transistor (TFT) and/or a metal-insulator-metal (MIM) capacitor is in the BEOL structure. The TFT and/or MIM capacitor is vertically over the zone that excludes MOS transistors.

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.

Abstract: IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.

Abstract: An example IC device includes a support structure; a device layer over or at least partially in the support structure, the device layer comprising transistors; and an interconnect layer. The device layer is between the support structure and the interconnect layer, and the interconnect layer includes a first conductive line and a second conductive line stacked above the first conductive line. A first end of the first conductive line is substantially aligned with a first end of the second conductive line along a plane perpendicular to the substrate, and a second end of the first conductive line is closer to the plane than a second end of the second conductive line. Such an arrangement of conductive lines may be referred to as “flipped staircase.

Abstract: An example IC device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. The plurality of areas includes a first area and a second area. The IC device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.

Abstract: A system for detecting a road surface includes a processor and a memory. The memory stores instructions executable by the processor to determine a virtual boundary for a vehicle body based on a shape of the vehicle body, to identify one or more objects based on vehicle sensor data, based on the identified one or more objects, the determined virtual boundary, and an input to at least one of propulsion, steering, or braking, to determine at least one of a braking override or a steering override, and based on the determination, to perform at least one of adjusting a vehicle steering and a vehicle speed.

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

Abstract: Disclosed herein are IC structures with three-dimensional capacitors with double metal electrodes provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example three-dimensional capacitor includes first and second capacitor electrodes and a capacitor insulator between them. Each capacitor electrode includes a planar portion extending across the support structure and one or more via portions extending into one or more via openings in the support structure. The capacitor insulator also includes a planar portion and a via portion extending into the via opening(s). The planar portion of the capacitor electrodes are thicker than the via portions. Each capacitor electrode may be deposited using two deposition processes, such as a conformal deposition process for depositing the via portion of the electrode, and a sputter process for depositing the planar portion of the electrode.

Abstract: A system for a smart building includes sensors configured to provide measurements using a plurality of communication protocols and an edge device, wherein the edge device provides a data bus, a plurality of protocol agents configured to ingest data from the plurality of sensors using the plurality of protocols and publish the data to the data bus, an analytics engine subscribed to the data on the data bus, and a plurality of containerized applications connected to the data bus.

Abstract: Systems and methods for collecting and displaying business insights in a cloud-based system. Steps include obtaining data from a cloud-based system associated with any of applications, infrastructure, and employees of an organization, wherein the cloud-based system includes a plurality of organizations with the applications, infrastructure, and employees each assigned thereto; processing the data associated with the organization to determine a plurality of insights; and displaying the plurality of insights on a per-organization basis based on the processing.

Abstract: One or more trained embedding generation artificial intelligence models are executed to generate a plurality of record attribute embeddings. The plurality of record attribute embeddings represents a plurality of attributes of data of a plurality of records. Grouping of the plurality of record attribute embeddings is performed. The grouping of a record attribute embedding includes grouping attribute values of the record attribute embedding into one or more groups of attribute values. The performing grouping provides a plurality of groups of attribute values for the plurality of record attribute embeddings. Selected records are compared to provide a set of matched records. The comparing, based on a group of attribute values, includes comparing records that include one or more attribute values grouped in the group of attribute values providing a subset of matched records of the set of matched records. The set of matched records is stored in an accessible computer location.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

Abstract: Methods, apparatus, and processor-readable storage media for automatically detecting data anomalies using artificial intelligence techniques are provided herein. An example computer-implemented method includes obtaining data pertaining to multiple tasks associated with at least one enterprise; detecting one or more data anomalies by predicting one or more values within the obtained data by processing at least a portion of the obtained data using one or more artificial intelligence techniques, and comparing the one or more predicted values to one or more corresponding portions of the obtained data; generating one or more data recommendations associated with at least a portion of the one or more detected data anomalies; and performing one or more automated actions based at least in part on at least one of the one or more detected data anomalies and the one or more generated data recommendations.

Abstract: Techniques are disclosed for framing images and/or video streams. Such techniques may include performing face detection on an image, determining a gaze direction within image content associated with a detected face, and defining a cropping window for the image based on the detected face and the determined gaze direction of the detected face. Thereafter, the image may be cropped according to the cropping window.

Abstract: Methods and systems are provided for monitoring the operation of a sucker rod pump (SRP), which involves a workflow that processes surface operational data and downhole operational data related to the operation of the SRP. The surface operational data is derived from real-time measurements performed by surface-located sensors, while the downhole operational data is derived from real-time measurements performed by downhole sensors. The surface operational data is processed to generate input data for supply to a first machine learning model (e.g., Surface Data Classifier) and the downhole operational data is processed to generate input data for supply to a second machine learning model (e.g., Downhole Data Classifier). The output of at least one of the first and second machine learning models is used to characterize an operational condition or status of the SRP.

Abstract: A method includes processing event data to detect a status of a network function. The event data is processed based on two or more conditions defined by a correlation policy. The correlation policy includes a non-deterministic finite automata tree (NFAT) structure correlation policy having a policy type and a logic-gate. The method additionally includes determining the policy type of the NFAT structure correlation policy. The method also includes determining whether a first value of the two or more conditions is indicative of whether a first condition is satisfied. The method further includes determining whether a second value of the two or more conditions is indicative of whether the second condition is satisfied. The method additionally includes determining whether the NFAT structure correlation policy is satisfied based on the first value, the second value, the logic-gate and the policy type.

Abstract: The physical characteristics of one or more anatomical structures of a person may change in accordance with conditions surrounding the determination of such physical characteristics. Machine learning based techniques may be used to determine a template representation of the one or more anatomical structures that may indicate the physical characteristics of the one or more anatomical structures free of the impact imposed by changing conditions. The template representation may then be used to predict the physical characteristics of the one or more anatomical structures under a new set of conditions, without subjecting the person to additional medical scans.

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.