Abstract: An air transferring system is disclosed. The air transferring system includes an enclosure, a faceplate, and a blower assembly attached to the faceplate. The enclosure includes a base, a lid having an air exhaust, and a shroud. The shroud has an open shroud top, an open shroud bottom, and an opening in the shroud defined between a first shroud edge and a second shroud edge. Each of the shroud edges extends between the open shroud top and the shroud bottom. The faceplate includes a faceplate opening that extends between the first and second shroud edges. The blower assembly includes a blower exhaust proximate to all of the faceplate opening, an exhaust opening, and an impeller for drawing air through the air exhaust, faceplate opening, and blower exhaust and urging the air out the exhaust.

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including an active region including a capacitor; and a metallization stack including a first conductive trace electrically coupled to a first conductor of the capacitor and a second conductive trace electrically coupled to a second conductor of the capacitor, wherein the first conductive trace and the second conductive trace are parallel to the first and second surfaces and exposed at the third surface; and a second IC die including a fourth surface, where the first conductive trace and the second conductive trace at the third surface of the first IC die are electrically coupled to the fourth surface of the second IC die by interconnects.

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface, wherein the conductive trace exposed at the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect.

Abstract: A computer includes a processor and a memory, the memory storing instructions executable by the processor to receive sensor data indicating an obstacle, formulate a control barrier function for a vehicle based on the sensor data, determine a control input based on the control barrier function, and actuate a component of the vehicle according to the control input. The control barrier function is defined with respect to a reference point that is spaced from a centroid of the vehicle.

Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

Abstract: A method can include implementing a control scheme for a plurality of wells; using the control scheme, classifying each of the wells; based on the classifying, identifying one or more of the wells as experiencing liquid loading; and issuing a control instruction to perform an unloading operation for the one or more of the wells.

Abstract: Approaches for controlling operations of a sucker rod pump system of a production well that produces reservoir fluids from a reservoir, which employs a gateway device disposed at a wellsite corresponding to the well and a cloud-computing system operably coupled to the gateway device. The gateway device may communicate time-series operational data characterizing operation of the sucker rod pump system to the cloud-computing system. The cloud-computing system can receive and store the time-series operational data communicated from the gateway device and repeatedly perform operations that i) process the time-series operational data to train a machine learning model that predicts run time of the sucker rod pump system given feature data extracted the time-series operational data and ii) use the resultant machine learning model to determine new operating parameter data for use in controlling the sucker rod pump system, wherein the new operating parameter data maximizes production from the well.

Abstract: A method, computer program, and computer system is provided for predicting data from an image. An image is divided into one or more patch images. Spatial features corresponding to the one or more patch images are compressed. Output data corresponding to the compressed spatial features is predicted. The output data is predicted based on minimizing one or more loss functions corresponding to the compressed spatial features.

Abstract: A correlation engine and policy manager (CPE) system includes: a persistent database, a cache database, an event gate, an event enricher, an event transformer, and an event dispatcher. The event gate obtains event data from at least one event source, and forwards the event data to the event enricher. The event enricher enriches the event data with additional data in the cached business layer data of the cache database, and forwards the enriched event data to the event transformer. The event transformer applies one or more policies in a cached business layer data of the cache database to the enriched event data to obtain transformed event data, and outputs the transformed event data to be stored in the persistent database. The event dispatcher dispatches output data to cause or prompt an action responsive to the transformed event data satisfying the at least one policy.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training a generative neural network. One of the methods includes training a generative neural network by performing a sequence of a plurality training stages each generating an expanded training data set. The method also involves performing a sequence of improve steps, each comprising training the generative neural network on the training examples in a corresponding subset of the expanded training data set.

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

Abstract: Disclosed herein are deep-learning based systems, methods, and instrumentalities for medical decision-making. A system as described herein may implement an artificial neural network (ANN) that may include multiple encoder neural networks and a decoder neural network. The multiple encoder neural networks may be configured to receive multiple types of patient data (e.g., text and image based patient data) and generate respective encoded representations of the patient data. The decoder neural network (e.g., a transformer decoder) may be configured to receive the encoded representations and generate a medical decision, a medical summary, or a medical questionnaire based on the encoded representations. In examples, the decoder neural network may be configured to implement a large language model (LLM) that may be pre-trained for performing the aforementioned tasks.

Abstract: Described are techniques for disintegrating an entity into smaller entities. A graph (“first graph”) for the entity of records to be disintegrated is constructed, where each vertex of the first graph represents a record in the entity of records to be disintegrated. The edges in the first graph connecting records in the entity of records represent matching links between the records, where each edge is associated with a weight corresponding to a similarity score. Furthermore, two or more additional graphs representing two or more sub-entities of the entity of records to be disintegrated are constructed. Such graphs are constructed based on selecting edges with a maximum weight out of the edges connected between each pair of records in the first graph or based on the number of connections each record has with other records in the first graph exceeding a threshold value.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

Abstract: Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

Abstract: An apparatus for automated collision avoidance includes a sensor configured to detect an object of interest, predicting a representation of the object of interest at a future point in time, calculating an indication of a possibility of a collision with the object of interest based on the representation of the object of interest at the future point in time, and executing a collision avoidance action based on the indication.

Abstract: Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memory are disclosed. An example IC device includes a floating body memory cell comprising a transistor having a first source or drain (S/D) region, a second S/D region, and a gate over a channel portion between the first and second S/D regions; a BL coupled to the first S/D region and parallel to a first axis of a Cartesian coordinate system; a SL coupled to the second S/D region and parallel to a second axis of the coordinate system; and a WL coupled to or being a part of the gate and parallel to a third axis of the coordinate system. IC devices implementing 3D floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced CMOS processes.