Abstract: A correlation engine and policy manager (CPE) system includes: a persistent database, a cache database, an event gate, an event enricher, an event transformer, and an event dispatcher. The event gate obtains event data from at least one event source, and forwards the event data to the event enricher. The event enricher enriches the event data with additional data in the cached business layer data of the cache database, and forwards the enriched event data to the event transformer. The event transformer applies one or more policies in a cached business layer data of the cache database to the enriched event data to obtain transformed event data, and outputs the transformed event data to be stored in the persistent database. The event dispatcher dispatches output data to cause or prompt an action responsive to the transformed event data satisfying the at least one policy.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training a generative neural network. One of the methods includes training a generative neural network by performing a sequence of a plurality training stages each generating an expanded training data set. The method also involves performing a sequence of improve steps, each comprising training the generative neural network on the training examples in a corresponding subset of the expanded training data set.

Abstract: Described are techniques for disintegrating an entity into smaller entities. A graph (“first graph”) for the entity of records to be disintegrated is constructed, where each vertex of the first graph represents a record in the entity of records to be disintegrated. The edges in the first graph connecting records in the entity of records represent matching links between the records, where each edge is associated with a weight corresponding to a similarity score. Furthermore, two or more additional graphs representing two or more sub-entities of the entity of records to be disintegrated are constructed. Such graphs are constructed based on selecting edges with a maximum weight out of the edges connected between each pair of records in the first graph or based on the number of connections each record has with other records in the first graph exceeding a threshold value.

Abstract: Disclosed herein are deep-learning based systems, methods, and instrumentalities for medical decision-making. A system as described herein may implement an artificial neural network (ANN) that may include multiple encoder neural networks and a decoder neural network. The multiple encoder neural networks may be configured to receive multiple types of patient data (e.g., text and image based patient data) and generate respective encoded representations of the patient data. The decoder neural network (e.g., a transformer decoder) may be configured to receive the encoded representations and generate a medical decision, a medical summary, or a medical questionnaire based on the encoded representations. In examples, the decoder neural network may be configured to implement a large language model (LLM) that may be pre-trained for performing the aforementioned tasks.

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

Abstract: Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.

Abstract: An apparatus for automated collision avoidance includes a sensor configured to detect an object of interest, predicting a representation of the object of interest at a future point in time, calculating an indication of a possibility of a collision with the object of interest based on the representation of the object of interest at the future point in time, and executing a collision avoidance action based on the indication.

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.

Abstract: Integrated circuit (IC) devices implementing three-dimensional (3D) floating body memory are disclosed. An example IC device includes a floating body memory cell comprising a transistor having a first source or drain (S/D) region, a second S/D region, and a gate over a channel portion between the first and second S/D regions; a BL coupled to the first S/D region and parallel to a first axis of a Cartesian coordinate system; a SL coupled to the second S/D region and parallel to a second axis of the coordinate system; and a WL coupled to or being a part of the gate and parallel to a third axis of the coordinate system. IC devices implementing 3D floating body memory as described herein may be used to address the scaling challenges of conventional memory technologies and enable high-density embedded memory compatible with advanced CMOS processes.

Abstract: Thin-film transistors and MIM capacitors in exclusion zones are described. In an example, an integrated circuit structure includes a semiconductor substrate having a zone with metal oxide semiconductor (MOS) transistors therein, and having a zone that excludes MOS transistors. A back-end-of-line (BEOL) structure is above the semiconductor substrate. A thin-film transistor (TFT) and/or a metal-insulator-metal (MIM) capacitor is in the BEOL structure. The TFT and/or MIM capacitor is vertically over the zone that excludes MOS transistors.

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

Abstract: An example IC device includes a support structure; a device layer over or at least partially in the support structure, the device layer comprising transistors; and an interconnect layer. The device layer is between the support structure and the interconnect layer, and the interconnect layer includes a first conductive line and a second conductive line stacked above the first conductive line. A first end of the first conductive line is substantially aligned with a first end of the second conductive line along a plane perpendicular to the substrate, and a second end of the first conductive line is closer to the plane than a second end of the second conductive line. Such an arrangement of conductive lines may be referred to as “flipped staircase.

Abstract: An example IC device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. The plurality of areas includes a first area and a second area. The IC device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.

Abstract: IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.

Abstract: A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.

Abstract: Disclosed herein are IC structures with three-dimensional capacitors with double metal electrodes provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example three-dimensional capacitor includes first and second capacitor electrodes and a capacitor insulator between them. Each capacitor electrode includes a planar portion extending across the support structure and one or more via portions extending into one or more via openings in the support structure. The capacitor insulator also includes a planar portion and a via portion extending into the via opening(s). The planar portion of the capacitor electrodes are thicker than the via portions. Each capacitor electrode may be deposited using two deposition processes, such as a conformal deposition process for depositing the via portion of the electrode, and a sputter process for depositing the planar portion of the electrode.

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

Abstract: A system for detecting a road surface includes a processor and a memory. The memory stores instructions executable by the processor to determine a virtual boundary for a vehicle body based on a shape of the vehicle body, to identify one or more objects based on vehicle sensor data, based on the identified one or more objects, the determined virtual boundary, and an input to at least one of propulsion, steering, or braking, to determine at least one of a braking override or a steering override, and based on the determination, to perform at least one of adjusting a vehicle steering and a vehicle speed.

Abstract: A system for a smart building includes sensors configured to provide measurements using a plurality of communication protocols and an edge device, wherein the edge device provides a data bus, a plurality of protocol agents configured to ingest data from the plurality of sensors using the plurality of protocols and publish the data to the data bus, an analytics engine subscribed to the data on the data bus, and a plurality of containerized applications connected to the data bus.