Patents by Inventor Abhishek Sharma

Abhishek Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120100
    Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 10, 2025
    Inventors: Sudipto NASKAR, Manish CHANDHOK, Abhishek A. SHARMA, Roman CAUDILLO, Scott B. CLENDENNING, Cheyun LIN
  • Publication number: 20250117959
    Abstract: Multiple predictions about the position of an object during a time period may each indicate the position of the object at a respective time during the time period. Respective validity indications corresponding to the multiple predictions may each indicate an accuracy of the corresponding prediction. Whether a change has occurred in a distribution of the predictions from a first subset of predictions to a second subset of predictions during the time period may be determined. If the change has occurred, a prediction from the first subset of predictions or the second subset of predictions may be selected, based on the validity of the predictions and/or the detection of a motion, as a best indication of the position of the object.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Applicant: Shanghai United Imaging Intelligence Co., Ltd.
    Inventors: Benjamin Planche, Ziyan Wu, Meng Zheng, Zhongpai Gao, Abhishek Sharma
  • Publication number: 20250116812
    Abstract: Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Wilfred Gomes
  • Patent number: 12271356
    Abstract: Described are techniques for disintegrating an entity into smaller entities. A graph (“first graph”) for the entity of records to be disintegrated is constructed, where each vertex of the first graph represents a record in the entity of records to be disintegrated. The edges in the first graph connecting records in the entity of records represent matching links between the records, where each edge is associated with a weight corresponding to a similarity score. Furthermore, two or more additional graphs representing two or more sub-entities of the entity of records to be disintegrated are constructed. Such graphs are constructed based on selecting edges with a maximum weight out of the edges connected between each pair of records in the first graph or based on the number of connections each record has with other records in the first graph exceeding a threshold value.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: April 8, 2025
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Seth, Soma Shekar Naganna, Mahendra Singh Kanyal, Devbrat Sharma
  • Patent number: 12271306
    Abstract: Three-dimensional (3D) DRAM integrated in the same package as compute logic enable forming high-density caches. In one example, an integrated 3D DRAM includes a large on-de cache (such as a level 4 (L4) cache), a large on-die memory-side cache, or both an L4 cache and a memory-side cache. One or more tag caches cache recently accessed tags from the L4 cache, the memory-side cache, or both. A cache controller in the compute logic is to receive a request from one of the processor cores to access an address and compare tags in the tag cache with the address. In response to a hit in the tag cache, the cache controller accesses data from the cache at a location indicated by an entry in the tag cache, without performing a tag lookup in the cache.
    Type: Grant
    Filed: March 27, 2021
    Date of Patent: April 8, 2025
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Adrian C. Moga, Abhishek Sharma
  • Patent number: 12265828
    Abstract: Methods, systems and computer program products are provided for automated runtime configuration for dataflows to automatically select or adapt a runtime environment or resources to a dataflow plan prior to execution. Metadata generated for dataflows indicates dataflow information, such as numbers and types of sources, sinks and operations, and the amount of data being consumed, processed and written. Weighted dataflow plans are created from unweighted dataflow plans based on metadata. Weights that indicate operation complexity or resource consumption are generated for data operations. A runtime environment or resources to execute a dataflow plan is/are selected based on the weighted dataflow and/or a maximum flow. Preferences may be provided to influence weighting and runtime selections.
    Type: Grant
    Filed: January 26, 2023
    Date of Patent: April 1, 2025
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Abhishek Uday Kumar Shah, Anudeep Sharma, Mark A. Kromer, Jikai Ma
  • Publication number: 20250105139
    Abstract: An example IC structure includes a first layer comprising a plurality of transistors; a second layer comprising a stack of layers of one or more insulator materials and conductive interconnect structures extending through the one or more insulator materials; a third layer comprising bonding pads, wherein the second layer is between the first layer and the third layer; and a via continuously extending between one of the bonding pads and one of the conductive interconnect structures in a bottom layer of the stack of layers or a conductive structure in the first layer, wherein the bottom layer is a layer of the stack of layers that is closer to the first layer than all other layers of the stack of layers.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventor: Abhishek A. Sharma
  • Publication number: 20250104760
    Abstract: An IC device may include memory layers over a logic layer. A memory layer includes memory arrays, each of which includes memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. Bit lines of different memory arrays may be coupled using one or more vias or source/drain electrodes of transistors in the memory arrays. Alternatively, word lines of different memory arrays may be coupled using one or more vias or gate electrodes of transistors in the memory arrays. The logic layer has a logic circuit that can control data read operations and data write operations of the memory layers. The logic layer may include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the memory device.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Anand S. Murthy, Tahir Ghani, Pushkar Sharad Ranade
  • Publication number: 20250107108
    Abstract: An IC device may include memory layers bonded to a logic layer with inclination. An angle between a memory layer and the logic layer may be in a range from approximately 0 to approximately 90 degrees. The memory layers may be over the logic layer. The IC device may include one or more additional logic layers that are parallel to a memory layer or perpendicular to a memory layer. The one or more additional logic layers may be over the logic layer. A memory layer may include memory cells. The logic layer may include logic circuits (e.g., sense amplifier, word line driver, etc.) that control the memory cells. Bit lines (or word lines) in different memory layers may be coupled to each other. A bit line and a word line in a memory layer may be controlled by logic circuits in different logic layers.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Tahir Ghani, Anand S. Murthy, Pushkar Sharad Ranade
  • Publication number: 20250107107
    Abstract: An IC device may include memory layers over a logic layer. A memory layer may include memory arrays and one or more peripheral circuits coupled to the memory arrays. A memory array may include memory cells arranged in rows and columns. A row of memory cells may be associated with a word line. A column of memory cells may be associated with a bit line. The logic layer includes one or more logic circuits that can control data read operations and data write operations of the memory layers. The logic layer may also include a power interconnect, which facilitates power delivery to the memory layers, and a signal interconnect, which facilitates signal transmission within the IC device. The IC device may further include vias that couple the memory layers to the logic layer. Each via may be connected to one or more memory layers and the logic layer.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sagar Suthram, Wilfred Gomes, Pushkar Sharad Ranade, Anand S. Murthy, Tahir Ghani
  • Publication number: 20250098179
    Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits with MOSFET transistors. The CMOS layer may also include memory cells, e.g., SRAM cells. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. A logic circuit in the CMOS layer may control access to the memory cells. A memory layer may be bonded with the CMOS layer through a bonding layer that includes conductive structures coupled to a logic circuit in the CMOS layer or to bit lines or word lines in the memory layer. An additional conductive structure may be at the backside of a MOSFET transistor in the CMOS layer and coupled to a conductive structure in the bonding layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Abhishek A. Sharma, Van H. Le, Fatih Hamzaoglu, Juan G. Alzate-Vinasco, Nikhil Jasvant Mehta, Vinaykumar Hadagali, Yu-Wen Huang, Honore Djieutedjeu, Tahir Ghani, Timothy Jen, Shailesh Kumar Madisetti, Jisoo Kim, Wilfred Gomes, Kamal Baloch, Vamsi Evani, Christopher Wiegand, James Pellegren, Sagar Suthram, Christopher M. Pelto, Gwang Soo Kim, Babita Dhayal, Prashant Majhi, Anand Iyer, Anand S. Murthy, Pushkar Sharad Ranade, Pooya Tadayon, Nitin A. Deshpande
  • Publication number: 20250095693
    Abstract: An IC device may include a CMOS layer and memory layers at the frontside and backside of the CMOS layer. The CMOS layer may include one or more logic circuits, which may include MOSFET transistors. A memory layer may include one or more memory arrays. A memory array may include memory cells (e.g., DRAM cells), bit lines, and word lines. The logic circuits may include word line drivers and sense amplifiers. Word lines in different memory layers may share the same word line driver. Bit lines in different memory layers may share the same sense amplifier. The IC device may include front-back word line drivers, near-far sense amplifiers, near-far word line drivers, or front-back sense amplifiers. A memory layer may be bonded with the CMOS layer through a bonding layer that provides a bonding interface between the memory layer and the CMOS layer.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Wilfred Gomes, Anand S. Murthy, Tahir Ghani, Van H. Le
  • Patent number: 12254543
    Abstract: The embodiments herein provide a system and method for personalized cartoon image generation. The method (100) comprises launching a keyboard interface (101), capturing a digital picture (102), face segmentation using neural network (103), normalization of segmented face (104), face cartoonification (105), which generates bobble head, facial landmark extraction (106), facial expression feature transfer (109) and customization of the generated plurality of cartoon images (110). Hence, the embodiments herein helps in creation of personalized plurality of cartoon images to make the user part of the conversations and the graphics or content shared look similar to the user input face and more aesthetically pleasing instead of using any reference stickers to convey the messages.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: March 18, 2025
    Assignee: Talent Unlimited Online Services Private Limited
    Inventors: Rahul Prasad, Abhishek Sharma, Mudit Rastogi
  • Publication number: 20250079399
    Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including an active region including a capacitor; and a metallization stack including a first conductive trace electrically coupled to a first conductor of the capacitor and a second conductive trace electrically coupled to a second conductor of the capacitor, wherein the first conductive trace and the second conductive trace are parallel to the first and second surfaces and exposed at the third surface; and a second IC die including a fourth surface, where the first conductive trace and the second conductive trace at the third surface of the first IC die are electrically coupled to the fourth surface of the second IC die by interconnects.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Applicant: Intel Corporation
    Inventors: Sagar Suthram, Wilfred Gomes, Ravindranath Vithal Mahajan, Debendra Mallik, Nitin A. Deshpande, Pushkar Sharad Ranade, Abhishek A. Sharma
  • Publication number: 20250075708
    Abstract: An air transferring system is disclosed. The air transferring system includes an enclosure, a faceplate, and a blower assembly attached to the faceplate. The enclosure includes a base, a lid having an air exhaust, and a shroud. The shroud has an open shroud top, an open shroud bottom, and an opening in the shroud defined between a first shroud edge and a second shroud edge. Each of the shroud edges extends between the open shroud top and the shroud bottom. The faceplate includes a faceplate opening that extends between the first and second shroud edges. The blower assembly includes a blower exhaust proximate to all of the faceplate opening, an exhaust opening, and an impeller for drawing air through the air exhaust, faceplate opening, and blower exhaust and urging the air out the exhaust.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 6, 2025
    Inventors: Chirag Sureshbhai Patel, Michael D. Smith, Steven A. Trimble, Surya Madugula, SaiGeetha Padiri, Jeffrey C. Hutson, Cameron Perini, Mitchell McDonald, Griffin Roach, Abhishek Sharma
  • Publication number: 20250079263
    Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface; and a second IC die having a fourth surface, wherein the conductive trace exposed at the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Applicant: Intel Corporation
    Inventors: Sagar Suthram, Debendra Mallik, Wilfred Gomes, Pushkar Sharad Ranade, Nitin A. Deshpande, Ravindranath Vithal Mahajan, Abhishek A. Sharma
  • Publication number: 20250079398
    Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Applicant: Intel Corporation
    Inventors: Sagar Suthram, Wilfred Gomes, Ravindranath Vithal Mahajan, Debendra Mallik, Pushkar Sharad Ranade, Nitin A. Deshpande, Abhishek A. Sharma
  • Patent number: 12238913
    Abstract: Described herein are two transistor (2T) memory cells that use TFTs as access and gain transistors. When one or both transistors of a 2T memory cell are implemented as TFTs, these transistors may be provided in different layers above a substrate, enabling a stacked architecture. An example 2T memory cell includes an access TFT provided in a first layer over a substrate, and a gain TFT provided in a second layer over the substrate, the first layer being between the substrate and the second layer (i.e., the gain TFT is stacked in a layer above the access TFT). Stacked TFT based 2T memory cells allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 25, 2025
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Juan G. Alzate-Vinasco, Fatih Hamzaoglu, Bernhard Sell, Pei-hua Wang, Van H. Le, Jack T. Kavalieros, Tahir Ghani, Umut Arslan, Travis W. Lajoie, Chieh-jen Ku
  • Patent number: 12233857
    Abstract: A computer includes a processor and a memory, the memory storing instructions executable by the processor to receive sensor data indicating an obstacle, formulate a control barrier function for a vehicle based on the sensor data, determine a control input based on the control barrier function, and actuate a component of the vehicle according to the control input. The control barrier function is defined with respect to a reference point that is spaced from a centroid of the vehicle.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: February 25, 2025
    Assignee: Ford Global Technologies, LLC
    Inventors: Mohit Srinivasan, Hongtei Eric Tseng, Michael Hafner, Mrdjan J. Jankovic, Abhishek Sharma, Erol Dogan Sumer, Alexander Jaeckel, Aakar Mehra
  • Publication number: 20250062278
    Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 20, 2025
    Applicant: Intel Corporation
    Inventors: Sagar Suthram, Debendra Mallik, Wilfred Gomes, Pushkar Sharad Ranade, Nitin A. Deshpande, Ravindranath Vithal Mahajan, Abhishek A. Sharma, Joshua Fryman, Stephen Morein, Matthew Adiletta, Michael Crocker, Aaron Gorius