Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Abstract: Application artifact registration is performed by receiving a bundle service specification configured for deployment of a software service in a cloud native environment, transferring a bundle from an original address indicated in the bundle service specification to an object storage at a principal address, attaching, to the bundle service specification, a bundle identifier and the principal address, extracting a plurality of artifacts from the bundle, each of the plurality of artifacts being stored in the object storage at a subordinate address, and creating one or more artifact service specifications, each artifact service specification representing one or more of the plurality of artifacts, each service specification representing the corresponding subordinate address, an artifact identifier, and an artifact type of each represented artifact.

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

Abstract: An example IC device formed using trim patterning as described herein may include a support structure, a first elongated structure (e.g., a first fin or nanoribbon) and a second elongated structure (e.g., a second fin or nanoribbon), proximate to an end of the first elongated structure. An angle between a projection of the first elongated structure on the support structure and an edge of the support structure may be between about 5 and 45 degrees, while an angle between a projection of the second elongated structure on the support structure and the edge of the support structure may be less than about 15 degrees.

Abstract: Top-gate thin film transistor (TFTs) structures. Thin film transistors when in the top-gate configuration suffer from contact resistance. An example TFT includes a semiconductor layer doped with one or more dopant elements. A gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. The semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. The TFT may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).

Abstract: Various arrangements for IC devices implementing memory with one access transistor for multiple capacitors are disclosed. An example IC device includes a memory array of M memory units, where each memory unit includes an access transistor and N capacitors coupled to the access transistor. A portion of the capacitors are formed in one or more layers above the access transistor, and a portion of the capacitors are formed in one or more layers below the access transistor. The capacitors in a particular memory unit may be coupled to a single via or to individual vias. In some embodiments, some of the vias are backside vias.

Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.

Abstract: The present disclosure provides a method for intelligent user localization in a metaverse, including: detecting movements of a wearable head gear configured to present virtual content to a user, and generating sensor data and visual data using an inertial sensor and a camera, respectively, mapping the visual data to a virtual world using an image associated with the visual data to localize the user in the virtual world; providing the visual data and the sensor data to a first Machine Learning (ML) model and a second ML model, respectively; extracting a plurality of key points from the visual data and distinguishing stable key points and dynamic key points; and removing visual impacts corresponding to the visual data having a relatively low weightage, and providing a relatively high weightage to the sensor data processed through the second ML model.

Abstract: Specified performance attributes may be used to configure machine learning transformations for ETL jobs. Performance attributes for a machine learning pipeline that applies a model to as part of a transformation for an ETL job may be used to configure a parameter in a stage of the machine learning pipeline. The configured stage may then be used when training the model. The trained machine learning pipeline may then be applied as part of a transformation operation included in an ETL job performed by the ETL system.

Abstract: Systems, methods and instrumentalities are described herein for automating a medical environment. The automation may be realized using one or more sensing devices and at least one processing device. The sensing devices may be configured to capture images of the medical environment and provide the images to the processing device. The processing device may determine characteristics of the medical environment based on the images and automate one or more aspects of the operations in the medical environment. These characteristics may include, e.g., people and/or objects present in the images and respective locations of the people and/or objects in the medical environment. The operations that may be automated may include, e.g., maneuvering and/or positioning a medical device based on the location of a patient, determining and/or adjusting the parameters of a medical device, managing a workflow, providing instructions and/or alerts to a patient or a physician, etc.

Abstract: Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

Abstract: Described herein are full wafer devices that include interconnect layers on a back side of the device. The backside interconnect layers couple together different dies of the full wafer device. The backside interconnect layers include an active layer that includes active devices, such as transistors. The active devices may act as switches, e.g., to control routing of signals between different dies of the full wafer device.

Abstract: Described herein are full wafer devices that include passive devices formed in a power delivery structure. Power is delivered to the full wafer device on a backside of the full wafer device. A passive device in a backside layer is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device.

Abstract: Use of observability data (metrics, logs, and traces) generated by a monitoring system that monitors a codebase of an organization computing system as code is executed is described herein, where the observability data is used to perform an operation pertaining to at least one of data privacy, data protection, or data governance.

Abstract: Described herein are full wafer devices that include passive devices formed in one or more interconnect layers. Interconnect layers are formed over a front side of the full wafer device. A passive device is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. In some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.

Abstract: A power management apparatus for a workflow to enable low power MR patient positioning on edge devices is disclosed. The power management apparatus changes an operational mode of an edge device from a first power mode to a second power mode after a defined time-interval. The power management apparatus further controls the edge device to capture a first image of a first scene. The power management apparatus further determines a trigger point based on a detection of a plurality of objects in the captured first image. The power management apparatus further changes the operational mode of the edge device from the second power mode to a third power mode to control a consumption of electric power while a set of operations is executed at the edge device. The operational mode of the edge device may be changed at the determined trigger point.

Abstract: A method for surgery planning is provided. The method may include: generating a surgery video displaying a process of a virtual surgery performed by a virtual surgical robot on a virtual patient based on a surgery plan relating to a robotic surgery to be performed on a patient by a surgical robot; transmitting the surgery video to a display component of an XR assembly used to render the surgery video for display to a user; recording one or more actions that the user performed on the virtual surgery based on user input received via an input component of the XR assembly; modifying the surgery plan based on the one or more recorded actions; and causing the surgical robot to implement the robotic surgery on the patient according to the modified surgery plan.

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

Abstract: The present disclosure provides a method for surgical automation. The method may include: obtaining video data generated in a surgical process using a camera; identifying a surgical stage in the surgical process based on the video data; and triggering an activation of a surgical equipment used for a surgical operation and/or providing a guidance of the surgical operation based on the surgical stage.