Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: Automatic hand gesture determination may be a challenging task considering the complex anatomy and high dimensionality of the human hand. Disclosed herein are systems, methods, and instrumentalities associated with recognizing a hand gesture in spite of the challenges. An apparatus in accordance with embodiments of the present disclosure may use machine learning based techniques to identify the area of an image that may contain a hand and to determine an orientation of the hand relative to a pre-defined direction. The apparatus may then adjust the area of the image containing the hand to align the orientation of the hand with the pre-defined direction and/or to scale the image area to a pre-defined size. Based on the adjusted image area, the apparatus may detect a plurality of hand landmarks and predict a gesture indicated by the hand based on the plurality of detected landmarks.

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.

Abstract: The present disclosure provides a system and a method for controlling motion of a bank of elevators. The method includes accepting current requests for service by the bank of elevators, accepting a partial trajectory of a motion of a person moving in an environment serviced by the bank of elevators, and obtaining a probability of a future elevator request. The method further includes processing the partial trajectory with a neural network trained to estimate a weighted combination of probability density functions that indicates an arrival time distribution of the person, and generating a set of possible future requests jointly representing the probability of the future elevator request and the arrival time distribution. The method further includes optimizing a schedule of the bank of elevators to serve the current requests and the set of possible future requests, and controlling the bank of elevators according to the schedule.

Abstract: Systems, computer program products, and methods are described herein for auto-scaling volatile memory allocation in an electronic network. The present invention is configured to access metadata of at least one volatile memory component, wherein the metadata is associated with at least one application; determine a current volatile memory allocation for the metadata; determine a current metadata format of the metadata; apply the metadata to a volatile memory allocation machine learning model; generate, based on the application of the metadata to the volatile memory allocation machine learning model, a new volatile memory allocation for the metadata; and apply the new volatile memory allocation to the metadata of the at least one volatile memory component, wherein the application of the new volatile memory allocation to the metadata comprises at least one of an upscaling, a downscaling, or a constant.

Abstract: An efficient state-machine-based pattern matching technique processes tokens in an input queue and identifies patterns in the sequence of tokens that match one or more predetermined input patterns without backtracking. Tokens can include data or no data and a time component. The tokens can be a stream of data generated by a sensor, which transforms a physical property into a digital quantity. The pattern matching technique processes the input queue in a single direction, and does not examine any previously examined token. In an implementation, specific patterns to be matched are specified using a state machine, where the state machine is specified in a state table and operates using a state stack.

Abstract: An edge computing platform with machine learning capability is provided between a local network with a plurality of sensors and a remote network. A machine learning model is created and trained in the remote network using aggregated sensor data and deployed to the edge platform. Before being deployed, the model is edge-converted (“edge-ified”) to run optimally with the constrained resources of the edge device and with the same or better level of accuracy. The “edge-ified” model is adapted to operate on continuous streams of sensor data in real-time and produce inferences. The inferences can be used to determine actions to take in the local network without communication to the remote network. A closed-loop arrangement between the edge platform and remote network provides for periodically evaluating and iteratively updating the edge-based model.

Abstract: A stacked-substrate FPGA device is described in which a second substrate is stacked over a first substrate. Logic transistors (e.g., semiconductor devices and at least some conductive interconnections between them) are generally fabricated on (or over) a first substrate and memory transistors (e.g., SRAM cells and SRAM arrays) are generally fabricated on a second substrate over the first substrate. This has the effect of physically disposing elements of a CLB and a programmable switch on two different substrates. That is a first portion of a CLB and a programmable switch corresponding to logic transistors are on a first substrate and a second portion of these components of an FPGA corresponding to SRAM transistors is on a second substrate.

Abstract: Systems, computer program products, and methods are described herein for auto-scaling volatile memory allocation in an electronic network. The present invention is configured to access metadata of at least one volatile memory component, wherein the metadata is associated with at least one application; determine a current volatile memory allocation for the metadata; determine a current metadata format of the metadata; apply the metadata to a volatile memory allocation machine learning model; generate, based on the application of the metadata to the volatile memory allocation machine learning model, a new volatile memory allocation for the metadata; and apply the new volatile memory allocation to the metadata of the at least one volatile memory component, wherein the application of the new volatile memory allocation to the metadata comprises at least one of an upscaling, a downscaling, or a constant.

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

Abstract: A computer includes a processor and a memory storing instructions executable by the processor to receive sensor data indicating a current position of an object, determine a predicted position of the object at a future time, and instruct a component of a vehicle to actuate based on the current position being in a first zone of a plurality of zones surrounding the vehicle and the predicted position being in a second zone of the plurality of zones different than the first zone. The zones are nonoverlapping and have preset boundaries relative to the vehicle.

Abstract: A system for providing performance optimization for a software solution may scan multiple predefined levels of the software solution to extract corresponding metadata information from each of the multiple predefined levels. The system may store the extracted corresponding metadata information pertaining to standard parameters associated with performance of the software solution. The system may determine a standard score based on a plurality of attributes of the extracted corresponding metadata information, optimize the determined standard score based on training data received from a learning model, and generate an insight information comprising information related to determined rule violations and of evaluation steps involved in determining the determined standard score.

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

Abstract: Integrated circuit structures having linerless self-forming barriers, and methods of fabricating integrated circuit structures having linerless self-forming barriers, are described. In an example, an integrated circuit structure includes a dielectric material above a substrate. An interconnect structure is in a trench in the dielectric material. The interconnect structure includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the dielectric material and with the conductive fill material. The 2D crystalline liner includes a same metal species as the conductive fill material.

Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

Abstract: The shape and/or location of an organ may change in accordance with changes in the body shape and/or pose of a patient. Described herein are systems, methods, and instrumentalities for automatically determining, using an artificial neural network (ANN), the shape and/or location of the organ based on human models that reflect the body shape and/or pose the patient. The ANN may be trained to learn the spatial relationship between the organ and the body shape or pose of the patient. Then, at an inference time, the ANN may be used to determine the relationship based on a first patient model and a first representation (e.g., a point cloud) of the organ so that given a second patient model thereafter, the ANN may automatically determine the shape and/or location of the organ corresponding to the body shape or pose of the patient indicated by the second patient model.

Abstract: Data samples are transmitted from a central server to at least one local server apparatus. The central server receives a set of predictions from the at least one local server apparatus that are based on the transmitted set of data samples. The central server trains a central model based on the received set of predictions. The central model, or a portion of the central model corresponding to a task of interest, can then be sent to the at least one local server apparatus. Neither local data from local sites nor trained models from the local sites are transmitted to the central server. This ensures protection and security of data at the local sites.