Abstract: A method includes processing event data to detect a status of a network function. The event data is processed based on two or more conditions defined by a correlation policy. The correlation policy includes a non-deterministic finite automata tree (NFAT) structure correlation policy having a policy type. The method also includes determining a first value of a first condition of the two or more conditions. The method further includes determining a second value of a second condition of the two or more conditions. The method additionally includes determining the policy type of the NFAT structure correlation policy. The method also includes determining whether the first value is greater than a first preset value indicative of whether the first condition is satisfied. The method further includes determining whether the second value is greater than a second preset value indicative of whether the second condition is satisfied.

Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The second IC die is between the first IC die and the package substrate. The first IC die includes: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is between the second IC die and the package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

Abstract: Automatically validating the calibration of an visual sensor network includes acquiring image data from visual sensors that have partially overlapping fields of view, extracting a representation of an environment in which the visual sensors are disposed, calculating one or more geometric relationships between the visual sensors, comparing the calculated one or more geometric relationships with previously obtained calibration information of the visual sensors, and verifying a current calibration of the visual sensors based on the comparison.

Abstract: Systems and methods are provided for monitoring and/or controlling operations of an artificial lift system of a production well, which employ a gateway device disposed at a wellsite corresponding to the well, and at least one remote cloud-computing system operably coupled to the gateway device. The gateway device includes at least one first interface to the artificial lift system, at least one second interface to the at least one cloud-computing system, and a processor configured to execute a first application that acquires data produced by the artificial lift system and communicated to the gateway device via the first interface.

Abstract: In some implementations, a device may receive extensibility data related to one or more custom code objects installed in a current environment. The device may classify the one or more custom code objects in one or more respective categories and determine one or more respective complexities associated with the one or more custom code objects based on the extensibility data. The device may generate an extensibility recommendation for deploying the one or more custom code objects to a target environment based on the one or more respective categories and the one or more respective complexities associated with the one or more custom code objects. The extensibility recommendation may be generated based on the one or more custom code objects satisfying extensibility conditions associated with the target environment. The device may provide an output relating to the extensibility recommendation.

Abstract: A system includes processing circuitry and a memory connected to the processing circuitry. The memory is configured to store executable instructions that, when executed by the processing circuitry, facilitate performance of operations. The operations include filtering, based upon business logic, business data within a cache database. Converting the filtered business data into a data model. Loading the data model to a persistent cache database. Obtaining event messages from a data source, where the event messages are generated by one or more state changes within a network operatively connected to the system. Obtaining, for an event message, event-related data from the data model, where the event-related data is topologically related to the event message. Combining the event message with the event-related data from the data model. Framing the event message with the event-related data; and route the frame according to a user-defined configuration file.

Abstract: A method that includes receiving an input at an interactive conversation service that uses an intent classification model. The method may further include generating, using an encoder model of the intent classification model, a set of output vectors corresponding to the input, where the encoder model is configured to determine a set of metrics corresponding to intent classifications. The method may further include determining, using an outlier detection model of the intent classification model, whether the input is in-domain or out-of-domain (OOD) based on a first vector of the set of output vectors satisfying a domain threshold relative to one or more of the intent classifications. The method may further include outputting, by the intent classification model, a second vector of the set of output vectors that indicates the set of metrics corresponding to the intent classifications or an indication that the input is OOD.

Abstract: A system includes a computer including a processor and a memory. The computer is programmed to determine a target location for a vehicle; based on a vehicle speed and a distance to the target location, determine a tunable acceleration parameter; determine a constraint, based on the tunable acceleration parameter, for a control barrier function to that outputs an acceleration to stop the vehicle at the target location; and upon solving the control barrier function to satisfy the constraint, actuate the vehicle to decelerate based on the acceleration output from the control barrier function.

Abstract: An edge computing platform with machine learning capability is provided between a local network with a plurality of sensors and a remote network. A machine learning model is created and trained in the remote network using aggregated sensor data and deployed to the edge platform. Before being deployed, the model is edge-converted (“edge-ified”) to run optimally with the constrained resources of the edge device and with the same or better level of accuracy. The “edge-ified” model is adapted to operate on continuous streams of sensor data in real-time and produce inferences. The inferences can be used to determine actions to take in the local network without communication to the remote network. A closed-loop arrangement between the edge platform and remote network provides for periodically evaluating and iteratively updating the edge-based model.

Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.

Abstract: A system performs named entity recognition for performing natural language processing, for example, for conversation engines. The system uses context information in named entity recognition. The system includes the context of a sentence during model training and execution. The system generates high quality contextual data for training NER models. The system utilizes labeled and unlabeled contextual data for training NER models. The system provides NER models for execution in production environments. The system uses heuristics to determine whether to use a context-based NER model or a simple NER model that does not use context information. This allows the system to use simple NER models when the likelihood of improving the accuracy of prediction based on context is low.

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

Abstract: Sensing device(s) may be installed in a medical environment to captures images of the medical environment, which may include an ultrasound probe and a patient. The images may be processed to determine, automatically, the position of the ultrasound probe relative to the patient's body. Based on the determined position, ultrasound image(s) taken by the ultrasound probe may be aligned with a 3D patient model and displayed with the 3D patient model, for example, to track the movements of the ultrasound probe and/or provide a visual representation of the anatomical structure(s) captured in the ultrasound image(s) against the 3D patient model. The ultrasound images may also be used to reconstruct a 3D ultrasound model of the anatomical structure(s).

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: The disclosure generally relates to method and system for autonomous vehicles management in an operating environment. The method may include sending a route plan in response to a request received by an autonomous vehicle from amongst a plurality of autonomous vehicles in an operating environment including one or more devices, wherein the one or more device comprises device or device space. The method may further include categorizing the route plan into path segments, the path segments including a first path segment including one or more nodes from the plurality of nodes being inside a device zone of the one or more devices and a second path segment including one or more nodes from the plurality of nodes being outside the device zone of the one or more devices.

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

Abstract: Image-based key points detection using a convolutional neural network (CNN) may be impacted if the key points are occluded in the image. Images obtained from additional imaging modalities such as depth and/or thermal images may be used in conjunction with RGB images to reduce or minimize the impact of the occlusion. The additional images may be used to determine adjustment values that are then applied to the weights of the CNN so that the convolution operations may be performed in a modality aware manner to increase the robustness, accuracy, and efficiency of key point detection.