Patents by Inventor Abhishek Sharma

Abhishek Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240051523
    Abstract: A computer includes a processor and a memory, the memory storing instructions executable by the processor to receive sensor data indicating an obstacle, formulate a control barrier function for a vehicle based on the sensor data, determine a control input based on the control barrier function, and actuate a component of the vehicle according to the control input. The control barrier function is defined with respect to a reference point that is spaced from a centroid of the vehicle.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 15, 2024
    Applicant: Ford Global Technologies, LLC
    Inventors: Mohit Srinivasan, Hongtei Eric Tseng, Michael Hafner, Mrdjan J. Jankovic, Abhishek Sharma, Erol Dogan Sumer, Alexander Jaeckel, Aakar Mehra
  • Publication number: 20240050006
    Abstract: The system comprises a prediction module (1) equipped with artificial intelligence to predict neurological disorders in an individual patient and identify a level of neurological disorders; a central processing unit (2) to detect triggering events and circumstances due to which the neurological disorders trigger in an individual patient upon receiving real-time behavior information data generated by a playing ball (3) of an individual patient and distinguish between a normal behavior and a neurological disorders behavior; an alert module (4) to alert the individual patient upon determining neurological disorders behavior; and an entertainment platform (5) to entertain and engage the individual patient with a specific set of activities assigned according to detected triggering events and circumstances upon determining the neurological disorders behavior, wherein a specific set of activities includes listening to music, playing games, and talking to an AI chatbot.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 15, 2024
    Inventors: Abhishek Sharma, Ahmed I. Alutaibi, Mohammed Alshehri, Sunil Kumar Sharma, Prateek Jain, Vikas Bajpai
  • Patent number: 11896408
    Abstract: Automated patient positioning and modelling includes a hardware processor to obtain image data from an imaging sensor, classify the image data, using a first machine learning model, as a patient pose based on one or more pre-defined protocols for patient positioning, provide a confidence score based on the classification of the image data and if the confidence score is less than a pre-determined value, re-classify the image data using a second machine learning model; or if the confidence score is greater than a pre-determined value, identify the image data as corresponding to a patient pose based on one or more pre-defined protocols for patient positioning during a scan procedure.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 13, 2024
    Assignee: Shanghai United Imaging Intelligence Co., LTD.
    Inventors: Meng Zheng, Abhishek Sharma, Srikrishna Karanam, Ziyan Wu
  • Publication number: 20240046536
    Abstract: The embodiments herein provide a system and method for personalized cartoon image generation. The method (100) comprises launching a keyboard interface (101), capturing a digital picture (102), face segmentation using neural network (103), normalization of segmented face (104), face cartoonification (105), which generates bobble head, facial landmark extraction (106), facial expression feature transfer (109) and customization of the generated plurality of cartoon images (110). Hence, the embodiments herein helps in creation of personalized plurality of cartoon images to make the user part of the conversations and the graphics or content shared look similar to the user input face and more aesthetically pleasing instead of using any reference stickers to convey the messages.
    Type: Application
    Filed: November 11, 2022
    Publication date: February 8, 2024
    Inventors: Rahul Prasad, ABHISHEK SHARMA, MUDIT RASTOGI
  • Patent number: 11880567
    Abstract: A request to perform a storage operation for a storage system is received. It is determined that the requested storage operation is associated with a policy that requires a quorum of approvals before being allowed to be performed. It is determined whether the quorum of approvals has been obtained. In response to a determination that the quorum of approvals has been obtained, a command to perform the requested operation is provided to the storage system.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: January 23, 2024
    Assignee: Cohesity, Inc.
    Inventors: Harsha Vardhan Jagannati, Abhishek Sharma
  • Patent number: 11881517
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: January 23, 2024
    Inventors: Abhishek Sharma, Cory Weber, Van H. Le, Sean Ma
  • Publication number: 20240006413
    Abstract: Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Tahir Ghani, Wilfred Gomes, Anand Murthy
  • Publication number: 20240008251
    Abstract: Integrated circuit dies, systems, and techniques are described herein related to one transistor-one capacitor dynamic random access memory. A memory device includes vertically aligned transistors having annular semiconductor structures and a shared bit line extending through the annular semiconductor structures, and vertically aligned capacitors having annular first capacitor plates, annular capacitor dielectric structures, and a shared second capacitor plate extending through the annular first capacitor plates, such that the annular first capacitor plates are in contact with corresponding ones of the annular semiconductor structures.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Tahir Ghani, Wilfred Gomes, Anand Murthy
  • Publication number: 20240006540
    Abstract: Techniques and mechanisms for providing epitaxial structures of an integrated circuit (IC). In an embodiment, an IC comprises a separation layer, and first and second channel stack structures at opposite surfaces of the separation layer. A first source or drain (SD) structure extends to the first channel stack structure, and a second SD structure extends to the second channel stack structure. A hole extends through the separation layer, wherein the first and second SD structures are formed concurrently by a deposition of an epitaxial (epi) material from one side of the hole. An insulator material of the separation layer facilitates separation of the first and second SD structures from each other during the epi deposition. In another embodiment, respective crystal orientations in the first and second SD structures each face the same direction along a vertical dimension which is orthogonal to the surfaces of the separation layer.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Anand Murthy, Tahir Ghani, Wilfred Gomes
  • Publication number: 20240008259
    Abstract: Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Tahir Ghani, Anand Murthy, Wilfred Gomes, Sagar Suthram
  • Publication number: 20240006415
    Abstract: Techniques and mechanisms for providing an integrated circuit (IC) which comprises an interconnect that extends between channel structures of two transistors. In an embodiment, a separation layer is provided between a first stack of channel structures and a second stack of channel structures, wherein an interior region of the separation layer comprises a sacrificial material which spans on overlap region between the stacks. Fabrication processes form a hole which exposes the interior region, and etching is performed to remove the sacrificial material from the separation layer. Subsequently, deposition processing forms in the interior region a trace portion of the interconnect. In another embodiment, the interconnect comprises a contiguous body of a conductor material, wherein the contiguous body extends to form respective regions of the trace portion, and a via portion of the interconnect.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek Sharma, Wilfred Gomes, Tahir Ghani, Anand Murthy
  • Patent number: 11862729
    Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek Sharma, Sean Ma, Van H. Le
  • Publication number: 20230414132
    Abstract: A system for providing rehabilitation in a virtual environment includes an extended reality (XR) headset to present a first rehabilitation therapy to a patient in a virtual environment. A sensing device is configured to track physical movements of the patient and a processor is configured to receive the sensing data to determine pose information. The processor is configured to determine a performance metric associated with the physical movements and compare the performance metric with a reference metric to determine whether the patient has successfully performed the defined physical movements. The processor is configured to change the first rehabilitation therapy to a second rehabilitation therapy based on a difference between the performance metric and the reference metric upon determining that the patient has unsuccessfully performed the defined physical movements. The system aids the patient by changing the rehabilitation therapies according to the performance of the patient.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Applicant: Shanghai United Imaging Intelligence Co., LTD.
    Inventors: Abhishek Sharma, Arun Innanje, Benjamin Planche, Meng Zheng, Shanhui Sun, Ziyan Wu, Terrence Chen
  • Patent number: 11849572
    Abstract: Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Sean T. Ma, Abhishek Sharma
  • Publication number: 20230399002
    Abstract: A system includes a processor and a memory. The memory stores instructions executable by the processor to determine a virtual barrier around a vehicle based on receiving a first user input and data indicating a vehicle sprung mass, upon receiving a second user input selecting the virtual barrier, to determine an updated virtual barrier based on the received second user input, upon determining the virtual barrier, to verify that the virtual barrier satisfies one or more vehicle parameters; and to provide output based on the virtual barrier.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Applicant: Ford Global Technologies, LLC
    Inventors: Erol Dogan Sumer, Abhishek Sharma, Mohit Srinivasan, Alexander Jaeckel, Michael Hafner, Mrdjan J. Jankovic, Aakar Mehra
  • Patent number: 11843058
    Abstract: Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: December 12, 2023
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Abhishek Sharma, Van Le, Jack Kavalieros, Shriram Shivaraman, Seung Hoon Sung, Tahir Ghani, Arnab Sen Gupta, Nazila Haratipour, Justin Weber
  • Patent number: 11843054
    Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 12, 2023
    Assignee: Intel Corporation
    Inventors: Van H. Le, Seung Hoon Sung, Benjamin Chu-Kung, Miriam Reshotko, Matthew Metz, Yih Wang, Gilbert Dewey, Jack Kavalieros, Tahir Ghani, Nazila Haratipour, Abhishek Sharma, Shriram Shivaraman
  • Patent number: 11844016
    Abstract: A network operating system (NOS) receives a bundle file transmitted from a vendor terminal of a vendor providing a network service, the bundle file including first data defining a functional unit group that achieves the network service and second data defining a monitoring policy for the network service. The NOS constructs the functional unit group based on the first data of the bundle file when the network service is purchased by a purchaser. The NOS executes a monitoring process on the functional unit group based on information on the functional unit group to be constructed and the second data of the bundle file.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 12, 2023
    Assignee: RAKUTEN SYMPHONY SINGAPORE PTE. LTD.
    Inventors: Shinya Kita, Puneet Devadiga, Rajat Singh, Bharath Rathinam, Abhishek Sharma, Rahul Atri
  • Patent number: 11827217
    Abstract: A computer is programmed to identify first and second virtual boundaries of a roadway lane based on a predicted boundary between the roadway lane and an adjacent roadway lane, determine a first constraint value based on a first virtual boundary approach acceleration, determine a second constraint value based on a second virtual boundary approach acceleration, output a prescribed steering angle, brake input, and propulsion input when one of the constraint values violates a respective threshold, and actuate components to attain the prescribed steering angle, brake input, and propulsion input. The first virtual boundary approach acceleration is based on a steering wheel angle of a vehicle and input to one of a brake or a propulsion of the vehicle. The second virtual boundary approach acceleration is based on a steering wheel angle of the vehicle and input to one of a brake or a propulsion of the vehicle.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 28, 2023
    Assignee: Ford Global Technologies, LLC
    Inventors: Michael Hafner, Mrdjan J. Jankovic, Yousaf Rahman, Abhishek Sharma, Mario Anthony Santillo
  • Publication number: 20230373471
    Abstract: A computer includes a processor and a memory, and the memory stores instructions executable by the processor to receive sensor data indicating an obstacle, formulate a control barrier function for a vehicle and the obstacle based on the sensor data, determine a control input based on the control barrier function and a combination function, and actuate a component of the vehicle according to the control input. The combination function is a sum of a first function weighted by a first weight and a second function weighted by a second weight, and the first weight and the second weight are based on a kinematic state of the obstacle.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Applicant: Ford Global Technologies, LLC
    Inventors: Abhishek Sharma, Michael Hafner, Mohit Srinivasan, Mrdjan J. Jankovic, Erol Dogan Sumer, Alexander Jaeckel, Aakar Mehra