Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190139192
    Abstract: Systems, apparatuses and methods may provide away to blend two or more of the scene surfaces based on the focus area and an offload threshold. More particularly, systems, apparatuses and methods may provide a way to blend, by a display engine, two or more of the focus area scene surfaces and blended non-focus area scene surfaces. The systems, apparatuses and methods may include a graphics engine to render the focus area surfaces at a higher sample rate than the non-focus area scene surfaces.
    Type: Application
    Filed: September 7, 2018
    Publication date: May 9, 2019
    Inventors: Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Prasoonkumar Surti
  • Publication number: 20190141358
    Abstract: Provided are mechanisms and processes for performing live filtering in a camera view via client-server communication. In one example, a first video frame in a raw video stream is transmitted from a client device to a server. The client device receives a filter processing message associated with the first video frame that includes filter data for applying a filter to the first video frame. A processor at the client device creates a filtered video stream by applying the filter to a second video frame that occurs in the video stream later than the first video frame.
    Type: Application
    Filed: August 7, 2018
    Publication date: May 9, 2019
    Applicant: Fyusion, Inc.
    Inventors: Stefan Johannes Josef Holzer, Matteo Munaro, Abhishek Kar, Alexander Jay Bruen Trevor, Krunal Ketan Chande, Radu Bogdan Rusu
  • Publication number: 20190138893
    Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip.
    Type: Application
    Filed: September 28, 2018
    Publication date: May 9, 2019
    Inventors: Abhishek SHARMA, Jack T. KAVALIEROS, Ian A. YOUNG, Ram KRISHNAMURTHY, Sasikanth MANIPATRUNI, Uygar AVCI, Gregory K. CHEN, Amrita MATHURIYA, Raghavan KUMAR, Phil KNAG, Huseyin Ekin SUMBUL, Nazila HARATIPOUR, Van H. LE
  • Patent number: 10283191
    Abstract: Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: May 7, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Abhishek Pathak, Tanmoy Roy, Shishir Kumar
  • Patent number: 10284221
    Abstract: A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: May 7, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Daniel Peter Canniff, Mariana Tosheva Markova, Edward Chapin Guthrie
  • Patent number: 10282812
    Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Altug Koker, Ingo Wald, David Puffer, Subramaniam M. Maiyuran, Prasoonkumar Surti, Balaji Vembu, Guei-Yuan Lueh, Murali Ramadoss, Abhishek R. Appu, Joydeep Ray
  • Patent number: 10281731
    Abstract: A 2D/3D switchable liquid crystal lens device includes: a polarization-dependent lens array, configured to provide a focusing effect for impinging light having a first plane of polarization of the impinging light and to provide no focusing effect for impinging light have a second plane of polarization orthogonal to the first plane of polarization; a switchable polarization rotating stage, comprising bi-stable liquid crystals, wherein the switchable polarization rotating stage is configured to output light having the first plane of polarization to the polarization-dependent lens array while the bi-stable liquid crystals are in a first state, and to output light having the second plane of polarization to the polarization-dependent lens array while the bi-stable liquid crystals are in a second state; and a driving system, configured to switch the bi-stable liquid crystals of the switchable polarization rotating stage between the first state and the second state.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 7, 2019
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE & TECHNOLOGY
    Inventors: Abhishek Kumar Srivastava, Vladimir Grigorievich Chigrinov, Hoi-Sing Kwok
  • Patent number: 10284440
    Abstract: A network monitoring system that summarizes a plurality of data packets of a session into a compact session record for storage and processing. Each session record may be produced in real-time and made available during the session and/or after the termination of the session. Depending on protocols, a network monitoring system extracts different sets of information, removes redundant information from the plurality of data packets, and adds performance information to produce the session record. The network monitoring system may retrieve and process a single session record or multiple session records for the same or different protocols to determine cause of events, resolve issues in a network or evaluate network performance or conditions. The session record enables analysis in the units of session instead of individual packets. Hence, the network monitoring system can analyze events, issues or performance of the network more efficiently and effectively.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: May 7, 2019
    Assignee: NetScout Systems, Inc
    Inventors: Anil K. Singhal, Bruce A. Kelley, Jr., Rajeev Nadkarni, Narendra Byrapuram, Abhishek Saraswati, Ashwani Singhal
  • Patent number: 10281713
    Abstract: A display device and a method for making the same are provided. In the method, source and drain contacts are patterned on a buffer layer. An IGZO layer is depositing over at least a portion of the source contact and a portion of the drain contact. A gate structure is formed over the IGZO layer. A silicon nitride layer is deposited over the gate structure and the IGZO layer to form a first doped region in the IGZO layer and a second doped region in the IGZO layer. A pixel electrode is formed over the buffer layer. A plurality of pixel walls are formed over the buffer layer, the plurality of pixel walls being associated with an electrowetting pixel and the pixel electrode being configured to a apply voltage within the electrowetting pixel. At least one of the source contact and the drain contact is connected to the pixel electrode.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 7, 2019
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Abhishek Kumar, Toru Sakai
  • Patent number: 10278675
    Abstract: Devices, systems, and methods for detecting estrus in subjects are provided. Devices include a housing configured for intravaginal/intrauterine deployment and retention and a sensor disposed in or on the housing, and are configured to use condition information sensed by the sensor to determine an estrus condition of the subject. Methods include deploying a device in the subject, sensing the condition information, and determining an estrus condition using the condition information. Systems include a device configured to communicate with a base station and/or with other implanted devices, which are located within a reception radius thereof, regarding the determined estrus condition.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 7, 2019
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: David Mathew Johnson, Scott A. Uhland, Ramkumar Abhishek, Robert Thomas Krivacic, Martin Sheridan
  • Patent number: 10282811
    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, Balaji Vembu
  • Patent number: 10284213
    Abstract: Some or all of a comparator circuit of an analog-to-digital converter (ADC) circuit can be efficiently repurposed or reused for residue amplification for efficient noise-shaping, e.g., in a noise-shaping feedback configuration. A preamplifier portion of a comparator circuit in an oversampling ADC can be re-purposed to provide an amplifier to amplify or otherwise modify a residue left after the bit trials of a conversion cycle. The amplified or modified residue can then be used elsewhere, for example, for noise-shaping by applying a noise transfer function (NTF), a result of which can then be fed back (e.g., summed with the next sampled input at an input of the comparator circuit for use in the N bit trials of the next ADC cycle).
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 7, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Abhishek Bandyopadhyay, Rong Jin
  • Publication number: 20190130101
    Abstract: Methods, apparatus, systems and articles of manufacture for detecting a side channel attack using hardware performance counters are disclosed. An example apparatus includes a hardware performance counter data organizer to collect a first value of a hardware performance counter at a first time and a second value of the hardware performance counter at a second time. A machine learning model processor is to apply a machine learning model to predict a third value corresponding to the second time. An error vector generator is to generate an error vector representing a difference between the second value and the third value. An error vector analyzer is to determine a probability of the error vector indicating an anomaly. An anomaly detection orchestrator is to, in response to the probability satisfying a threshold, cause the performance of a responsive action to mitigate the side channel anomaly.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Li Chen, Abhishek Basak, Salmin Sultana, Justin Gottschlich
  • Publication number: 20190129574
    Abstract: Disclosed are examples of systems, apparatus, methods and computer program products for attaching customizable widgets to feed items. A publisher can be displayed on a display of a device. The publisher can comprise an input area capable of receiving text, a first selection operable to cause the text to be shared in a feed as a feed item, and a second selection operable to cause a customizable widget to be attached to the feed item. The customizable widget can comprise an interactive presentation of information. The interactive presentation of the information can be configurable to be automatically modified in response to occurrence of updates associated with the information when the customizable widget is displayed as an attachment to the feed item, and the customizable widget can be configurable to be customized by authorized users of the social networking system.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventors: Abhishek Gupta, Bhavana Rehani, Viraj Turakhia, Runying Mao, Xiaojin Wang
  • Publication number: 20190129252
    Abstract: A photoaligned quantum rod enhancement film (QREF) includes: a substrate (802, 805); a photoalignment layer deposited on the substrate (802, 805); and a polymer layer deposited on the photoalignment layer, the polymer layer comprises a plurality of quantum rods, the plurality of quantum rods are configured to emit one or more wavelengths of light in response to pumping light, and are aligned to an alignment axis based on the photoalignment layer.
    Type: Application
    Filed: May 10, 2017
    Publication date: May 2, 2019
    Applicant: The Hong Kong University of Science and Technology
    Inventors: Abhishek Kumar SRIVASTAVA, Wanlong ZHANG, Vladimir Grigorievich CHIGRINOV, Hoi Sing KWOK
  • Publication number: 20190130585
    Abstract: An automated motion-blur detection process can detect frames in digital videos where only a part of the frame exhibits motion blur. Certain embodiments programmatically identify a plurality of feature points within a video clip, and calculate a speed of each feature point within the video clip. A collective speed of the plurality of feature points is determined based on the speed of each feature point. A selection factor is compared to a selection threshold for each video frame. The selection factor is based at least in part on the collective speed of the plurality of feature points. Based on this comparison, at least one video frame from within the video clip is selected. In some aspects, the selected video frame is relatively free of motion blur, even motion blur that occurs in only a part of the image.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 2, 2019
    Inventors: Sagar Tandon, Abhishek Shah
  • Publication number: 20190130038
    Abstract: A network crawler crawls one or more media sites to extract a plurality of titles for information contained in the one or more media sites. For example, the network crawler may extract the titles on the one or more media sites by identifying different computer formats and converting the titles in the different computer formats into a common computer format for comparison. User profiles which, includes user's interest are stored in a user profile interest database. A novel personalized news recommendation engine recommends news similar to the interest specified in a user profile, where maximum weighted matching is applied to score the similarity of news against user interest in the word2vec space.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 2, 2019
    Inventors: Fei Xiao, Christopher Li, Zhou Xing, Marzieh Parandehgheibi, Christopher F. Pouliot, Nilesh V. Kulkarni, Abhishek Singhal, Edward H. Baik, Lisa E. Falkson
  • Publication number: 20190132724
    Abstract: This disclosure generally relates to systems, devices, apparatuses, products, and methods for signaling communication characteristics between wireless devices. In one implementation, a first wireless communication device may determine that a trigger frame will allocate one or more resource units for communications by one or more stations unassociated with the first wireless communication device. The first wireless communication device adds an indication of a reference channel associated with the first wireless communication device or a basic service set (BSS) color indication to the trigger frame. The trigger frame is output for transmission to one or more other wireless communication devices. A receiving device may then identify the reference channel or the BSS color indication from the trigger frame and use this information for communication with the first wireless communication device.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 2, 2019
    Inventors: Alfred ASTERJADHI, Abhishek Pramod PATIL, George CHERIAN, Bin TIAN
  • Publication number: 20190132603
    Abstract: One embodiment provides for a general-purpose graphics processor comprising a multisample antialiasing compression module to perform planar multi-sample anti-aliasing, the multisample antialiasing compression module to analyze color data for a set of sample locations of a first pixel; determine a first plane to allocate for the first pixel, wherein the first plane is a lowest order plane to be allocated for the first pixel; and merge a plane allocation for the first pixel with a plane allocation for a second pixel in response to a determination that the first plane is the lowest order plane to be allocated for the second pixel.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 2, 2019
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
  • Publication number: 20190128073
    Abstract: A cutting element assembly may include a support structure and a pin having a cylindrical exterior bearing surface. Retention elements may couple opposing ends of the pin to the support structure. The cutting element assembly also includes a rotatable cutting element including a table of polycrystalline hard material having an end cutting surface and a supporting substrate. The rotatable cutting element may have an interior sidewall defining a longitudinally extending through hole. The pin may be positioned within the through hole of the rotatable cutting element and may be supported on the opposing ends thereof by the support structure. Methods include drilling a subterranean formation including engaging a formation with one or more of the rotatable cutting elements.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventors: John Abhishek Raj Bomidi, Jon David Schroder, Kegan L. Lovelace, William A. Moss, JR., Alexander Rodney Boehm