Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10250446
    Abstract: The disclosed technology relates to a distributed policy store. A system is configured to locate, in an index, an entry for a network entity, determine, based on the entry, a file identifier for a file containing a record for the network entity and an offset indicating a location of the record in the file. The system is further configured to locate the file in a distributed file system using the file identifier, locate the record in the file using the offset, and retrieve the record.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 2, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Rohit Prasad, Shashi Gandham, Hai Vu, Varun Malhotra, Sunil Gupta, Abhishek Singh, Navindra Yadav, Ali Parandehgheibi, Ravi Prasad, Praneeth Vallem, Paul Lesiak, Hoang Nguyen
  • Publication number: 20190096117
    Abstract: One embodiment provides a graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample anti-aliasing, the hardware graphics rendering pipeline including pixel processing logic to determine that each sample location of a pixel of a multisample surface is associated with a clear value and resolve a color value for the pixel to a non-multisample surface via a write of metadata to indicate that the pixel has the clear value.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Devan Burke, Abhishek Venkatesh, Travis Schluessler
  • Publication number: 20190098532
    Abstract: A method performed by a device that has a current first network connection to a first network. The device determining one or more current conditions associated with the device, determining whether a disconnect of the first network connection is imminent based on the one or more current conditions and responsive to determining that the disconnect is imminent, performing a pre-fetch operation to request data over the first network connection for at least one application resident on the device.
    Type: Application
    Filed: May 2, 2018
    Publication date: March 28, 2019
    Inventors: Abhishek RAWAT, Chaitanya MANNEMALA
  • Publication number: 20190096024
    Abstract: Embodiments are generally directed to area-efficient implementations of graphics instructions. An embodiment of an apparatus includes a graphics subsystem, the graphics subsystem including one or more of a first logic for processing of memory read-return data for single-instruction-multiple-data instructions, the first logic to store data for a message in raw data format and delay conversion into shader format until all cache line requests for the message have been received; a second logic for assembly of memory read-return data for media block instructions into shader register format, the logic to provide for storage of valid bytes from a cache fragment in a register; or a third logic to remap scatter or gather instructions to untyped surface instruction types.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Prasoonkumar Surti, Abhishek R. Appu, Altug Koker, Vasanth Ranganathan
  • Publication number: 20190095457
    Abstract: A B?-tree associated with a file system on a storage volume includes a hierarchy of nodes. Each node includes a buffer portion that can be characterized by a fixed maximum allowable size to store key-value pairs as messages in the buffer. Messages can be initially buffered in the root node of the B?-tree, and flushed to descendent children from the root node. Messages stored in the buffers can be indexed using a B+-tree data structure. As the B+-tree data structure in a buffer grows (due to receiving flushed messages) and shrinks (due to messages being flushed), disk blocks can be allocated from the storage volume to increase the actual size of the buffer and deallocated from the buffer to reduce the actual size of the buffer.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Abhishek Gupta, Richard P Spillane, Kapil Chowksey, Wenguang Wang, Robert T Johnson
  • Publication number: 20190098565
    Abstract: Methods and systems for accessing networks prohibit uncontrolled communications over a designated network. In some aspects, a method of controlling network access is disclosed. The method comprises transmitting, by a first access point, a first beacon over a first network to a station, the first beacon including information allowing the station to associate with the first access point. The method also comprises receiving a probe request at the first access point over the first network from the station, the probe request including a request for rules for associating with a second network. The method additional comprises generating a probe response to include the rules regarding associating with the second network, wherein the rules do not permit uncontrolled communications over the second network. The method further comprises transmitting the probe response from the first access point to the station over the first network.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Inventors: George Cherian, Alfred Asterjadhi, Abhishek Pramod Patil
  • Publication number: 20190095703
    Abstract: A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Barnan Das, Mayuresh M. Varerkar, Narayan Biswal, Stanley J. Baran, Gokcen Cilingir, Nilesh V. Shah, Archie Sharma, Sherine Abdelhak, Praneetha Kotha, Neelay Pandit, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Abhishek R. Appu, Altug Koker, Joydeep Ray
  • Publication number: 20190095469
    Abstract: Embodiments are generally directed to area-efficient implementations of graphics instructions. An embodiment of an apparatus includes one or more processors to process data, including generating multiple sets of data including at least a first data set and a second data set for a data application; a memory for the storage of data; and a delta compression engine, the delta compression engine being operable to perform a selected delta compression operation on the generated plurality of sets of data. The delta compression operation includes multiple orders of delta compression to be performed on the second data set based on differences with the first data set, the orders of delta compression including a first order delta and a second order delta. Each of the orders of delta compression includes one of multiple data encoding processes, the data encoding processing including a first data encoding process and a second, different data encoding process.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Kiran C. Veernapu, Abhishek R. Appu, Prasoonkumar Surti
  • Publication number: 20190090859
    Abstract: A urine capturing arrangement is configured to receive urine from a user of a toilet, and a chamber is fluidically coupled to the capturing arrangement. A diverter is fluidically coupled between the capturing arrangement and the chamber. The diverter is configured to divert a volume of the received urine to the chamber. A detection unit is configured to sense for presence of a predetermined characteristic in the volume of the urine and to generate at least one electrical signal comprising information about the predetermined characteristic.
    Type: Application
    Filed: November 27, 2018
    Publication date: March 28, 2019
    Inventors: Michael I. Recht, Joerg Martini, Abhishek Ramkumar, Peter Kiesel, Ben Hsieh, Eugene M. Chow
  • Publication number: 20190096095
    Abstract: An apparatus and method for pre-decompression filtering of compressed texel data.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: KIRAN C. VEERNAPU, BENJAMIN R. PLETCHER, YOAV HAREL, SANTOSH SANGUMANI, PRASOONKUMAR SURTI, ABHISHEK R. APPU
  • Publication number: 20190095292
    Abstract: A digital medium environment is described for automatic design discrepancy reporting of discrepancies between an actual display and its intended design. In one example, a design validation system generates a design screen model for a design screen, based on an object included in the design screen and at least one display property that defines a visual appearance of the object. The design validation system then identifies an application object that has a similar visual appearance to the defined visual appearance of the object of the design screen model. The design validation system additionally determines that a discrepancy exists between a display of the design screen model object and the application object. The design validation system also determines a value by which the at least one property of the application object is to be adjusted and outputs the value to adjust the at least one display property of the application object.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Applicant: Adobe Systems Incorporated
    Inventors: Shashidhar Mangu, Shamit Kumar Mehta, Nikhil Gupta, Abhishek Garg
  • Publication number: 20190094294
    Abstract: Monolithic three-dimensional integration can achieve higher device density compared to 3D integration using through-silicon vias. A test solution for M3D integrated circuits (ICs) is based on dedicated test layers inserted between functional layers. A structure includes a first functional layer having first functional components of the IC with first test scan chains and a second functional layer having second functional components of the IC with second test scan chains. A dedicated test layer is located between the first functional layer and the second functional layer. The test layer includes an interface register controlling signals from a testing module to one of the first test scan chains and the second test scan chains, and an instruction register connected to the interface register. The instruction register processes testing instructions from the testing module. Inter-layer vias connect the first functional components, the second functional components, and the testing module through the test layer.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 28, 2019
    Applicants: Duke University
    Inventors: Sukeshwar Kannan, Abhishek Koneru, Krishnendu Chakrabarty
  • Publication number: 20190095460
    Abstract: A B?-tree associated with a file system on a storage volume includes a hierarchy of nodes. Each node includes a buffer portion to store key-value pairs as messages in the buffer. Each node can be characterized by having a maximum allowable size that is periodically updated at run time. The buffers in the nodes of the B?-tree are therefore characterized by having a maximum allowed size that can vary over time.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Wenguang Wang, Abhishek Gupta, Richard P Spillane, Kapil Chowksey, Robert T Johnson
  • Publication number: 20190095327
    Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M Cimini, Abhishek R. Appu
  • Patent number: 10242955
    Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Mohit Arora, Kumar Abhishek, Prashant Bhargava, Rakesh Pandey
  • Patent number: 10240283
    Abstract: The present invention relates to textile fabrics and methods of manufacturing textile fabrics. Particularly, the invention comprises a method of producing a fabric, comprising the steps of (i) blending chemo mechanically felting fibers with non-felting fibers into a blended feed material, (ii) spinning the blended feed material into a blended yarn, (iii) producing a fabric comprising the blended yarn, (iv) subjecting the fabric to a first fabric treatment comprising a mechanical felting treatment; and (v) subjecting the fabric to a second fabric treatment comprising a chemical treatment of the fabric with an alkali, wherein the ratio of weight of the alkali to dry fabric weight is between 0.02 and 0.05, thereby obtaining increased air space in the resultant fabric.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: March 26, 2019
    Assignee: Trident Limited
    Inventors: Abhishek Gupta, Swadesh Kumar
  • Patent number: 10241776
    Abstract: Changing user settings across applications and/or across devices via a dialog within one application is provided herein. The systems and methods discussed herein provide for an improved user experience and fewer computing resources to be expended when changing user settings by aggregating the changeable settings, allowing for their modification via a single dialog, and distributing settings changes to remote hosts, which in turn provide consistent settings across devices. The settings available to the user may be governed in association with the user's licenses to access programs and may be affected by domain level controls by an administrator.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: March 26, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Abhishek Kumar, Gargee Sharma, Subash Kumar Bhamidipati, Ananthakrishnan Ramanathan, Matthew Carlo Razza, Vidya Kotteri, Ying Zhe Chong, Cancan Shi, Bhanu Samyal
  • Patent number: 10242423
    Abstract: One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, the multiprocessors to execute at least one single instruction; the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions; and the floating-point operation is a two-dimensional matrix multiply and accumulate operation.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Elmoustapha Ould-Ahmed-Vall, Sara S. Baghsorkhi, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker, Abhishek R. Appu, John C. Weast, Mike B. Macpherson, Dukhwan Kim, Linda L. Hurd, Ben J. Ashbaugh, Barath Lakshmanan, Liwei Ma, Joydeep Ray, Ping T. Tang, Michael S. Strickland
  • Patent number: 10242754
    Abstract: A method and system for providing therapy to an individual, the method comprising: transmitting a log of use dataset associated with communication behavior of the individual during a time period; receiving a supplementary dataset characterizing mobility of the individual in association with the time period; generating a survey dataset upon retrieving responses provided by the individual to at least one of a set of surveys, associated with a set of time points of the time period; generating a predictive model from a passive dataset derived from the log of use dataset and the supplementary dataset and the survey dataset; generating a report summarizing a mental health state of the individual, associated with at least a portion of the time period, from the passive dataset, the survey dataset, and an output of the predictive model; and rendering information from the report to a coach associated with the individual.
    Type: Grant
    Filed: November 18, 2017
    Date of Patent: March 26, 2019
    Assignee: Ginger.io, Inc.
    Inventors: Sai Moturu, Anmol Madan, Karan Singh, Abhishek Nath, Amanda Withrow, Aditya Sharma
  • Patent number: 10241921
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 26, 2019
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Prasoonkumar Surti, Kamal Sinha, Kiran C. Veernapu, Balaji Vembu