Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Eviction control for an address translation cache
    Patent number: 10102143
    Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 16, 2018
    Assignee: ARM Limited
    Inventors: Barry Duane Williamson, Michael Filippo, . Abhishek Raja, Adrian Montero, Miles Robert Dooley
  • Shared scene mesh data synchronisation
    Patent number: 10104415
    Abstract: A user device within a communication architecture, the user device comprising: an image capture device configured to determine image data for the creation of a video channel defining the shared scene; an intrinsic/extrinsic data determiner configured to determine intrinsic/extrinsic capture device data associated with the image capture device; and a video encoder configured to encode the image data and intrinsic/extrinsic capture device data within the video channel.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: October 16, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ming-Chieh Lee, Mei-Hsuan Lu, Robert Aichner, Ryan S. Menezes, Abhishek Abhishek, Bofan Hsu, Ermin Kozica
  • Auto discovery and configuration of services in a load balancing appliance
    Patent number: 10101981
    Abstract: The present disclosure is directed towards systems and methods for managing application delivery in a network. A device intermediary to a client and one or more servers that provide a plurality of applications, receives a request from the client to access a first application of the plurality of applications. The device holds the request and retrieves, while holding the request, configuration information for an instance of the first application from a configuration repository. The device configures a virtual internet protocol (“VIP”) server using the configuration information for the instance of the first application. The device processes the request via the VIP server.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 16, 2018
    Assignee: Citrix Systems, Inc.
    Inventors: Mahesh Arumugam, Sergey Verzunov, Sandeep Kamath, Josephine Suganthi, Anil Shetty, Abhishek Chauhan
  • Structurally embedded lighting for display panels and method of making the same
    Patent number: 10099800
    Abstract: A method and an apparatus for forming an embedded light source in a composite panel. A first electrode and a second electrode are associated with a first layer of material. A light source is positioned in electrical communication with the first electrode and the second electrode. An assembly comprising the first layer of material, the first electrode, the second electrode, and the light source is processed to form a multilayer panel with an embedded light source.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: October 16, 2018
    Assignee: The Boeing Company
    Inventors: Abhishek Pradeep Kulkarni, John Christopher Wilde, Xiaoxi Wang, Nathanial C. Cuddy
  • Systems and methods for driver and vehicle tracking
    Patent number: 10101163
    Abstract: Systems and method are provided for tracking locations of a driver and vehicle. In one example, a location tracking system pairs a vehicle location device and a driver location device by associating a driver identifier and a timestamp with the driver location device and the vehicle location device, obtains vehicle location data including a set of vehicle location data points, obtains driver location data including a set of driver location data points, correlates the vehicle location data and the driver location data, generates vehicle driver data based on the correlated vehicle location data and driver location data, and identifies a driver of the vehicle at a particular time by using the vehicle driver data and the timestamp.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 16, 2018
    Assignee: CALAMP CORP
    Inventor: Abhishek
  • Multi-user search system using tokens
    Patent number: 10102238
    Abstract: A multi-user search system with methodology for instant indexing. In one embodiment, for example, a system for instant indexing includes a token store storing sets of tokens for current versions of documents.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 16, 2018
    Assignee: Dropbox, Inc.
    Inventors: Samir Goel, Franck Chastagnol, Abhishek Agrawal
  • CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER
    Publication number: 20180293760
    Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Hugues Labbe, Atsuo Kuwahara, Sameer Kp, Jonathan Kennedy, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh
  • SMART COMPRESSION/DECOMPRESSION SCHEMES FOR EFFICIENCY AND SUPERIOR RESULTS
    Publication number: 20180293778
    Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.
    Type: Application
    Filed: April 9, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Kiran C. Veernapu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay
  • APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE
    Publication number: 20180293690
    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: JOYDEEP RAY, ABHISHEK R. APPU, ALTUG KOKER, BALAJI VEMBU
  • EXTENDED LOCAL MEMORY INCLUDING COMPRESSED ON-CHIP VERTEX DATA
    Publication number: 20180293703
    Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Karthik Vaidyanathan, Prasoonkumar Surti, Michael Apodaca, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Abhishek R. Appu
  • INDEPENDENT AND SEPARATE ENTITY-BASED CACHE
    Publication number: 20180293170
    Abstract: A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Joydeep Ray, James A. Valerio, Abhishek R. Appu, Vasanth Ranganathan
  • EFFICIENT THREAD GROUP SCHEDULING
    Publication number: 20180293102
    Abstract: A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.
    Type: Application
    Filed: April 9, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Abhishek R. Appu, Altug Koker, Kamal Sinha, Balaji Vembu, Rajkishore Barik, Eriko Nurvitadhi, Nicolas C. Galoppo Von Borries, Tsung-Han Lin, Sanjeev Jahagirdar, Vasanth Ranganathan
  • Frequent Data Value Compression for Graphics Processing Units
    Publication number: 20180293695
    Abstract: A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Saurabh Sharma, Abhishek Venkatesh, Travis T. Schluessler, Prasoonkumar Surti, Altug Koker, Aravindh V. Anantaraman, Pattabhiraman P. K., Abhishek R. Appu, Joydeep Ray, Kamal Sinha, Vasanth Ranganathan, Bhushan M. Borole, Wenyin Fu, Eric J. Hoekstra, Linda L. Hurd
  • GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE
    Publication number: 20180293205
    Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
    Type: Application
    Filed: April 9, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Farshad Akhbari, Feng Chen, Dukhwan Kim, Narayan Srinivasa, Nadathur Rajagopalan Satish, Liwei Ma, Jeremy Bottleson, Eriko Nurvitadhi, Joydeep Ray, Ping T. Tang, Michael Strickland, Xiaoming Chen, Tatiana Shpeisman, Abhishek R. Appu
  • DUAL PATH SEQUENTIAL ELEMENT TO REDUCE TOGGLES IN DATA PATH
    Publication number: 20180293780
    Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Sanjeev S. Jahagirdar, Kiran C. Veernapu, Eric J. Asperheim, Altug Koker, Balaji Vembu, Joydeep Ray, Abhishek R. Appu
  • COARSE GRAIN COHERENCY
    Publication number: 20180293693
    Abstract: One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
    Type: Application
    Filed: April 9, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, James A. Valerio, David Puffer, Abhishek R. Appu, Stephen Junkins
  • ADJUSTING GRAPHICS RENDERING BASED ON FACIAL EXPRESSION
    Publication number: 20180292895
    Abstract: An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Jefferson Amstutz, Carson Brownlee, Vivek Tiwari, Sayan Lahiri, Kai Xiao, Abhishek R. Appu, ElMoustapha Ould-Ahmed-Vall, Deepak S. Vembar, Ankur N. Shah, Balaji Vembu, Josh B. Mastronarde
  • Dynamic Page Sizing of Page Table Entries
    Publication number: 20180293702
    Abstract: In accordance with one embodiment each page table entry maps a variable page size (per entry), if multiple continuous virtual pages map to contiguous physical pages. This may drastically reduce the number of translation lookaside buffer (TLB) entries needed since each entry can potentially map a larger chunk of memory, in some embodiments.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Abhishek R. Appu, Joydeep Ray, Altug Koker, Balaji Vembu, Prasoonkumar P. Surti, Kamal Sinha, Vasanth Ranganathan, Kiran C. Veernapu, Bhushan M. Borole, Wenyin Fu
  • PRE-PASS SURFACE ANALYSIS TO ACHIEVE ADAPTIVE ANTI-ALIASING MODES
    Publication number: 20180293696
    Abstract: Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.
    Type: Application
    Filed: April 10, 2017
    Publication date: October 11, 2018
    Inventors: Abhishek R. Appu, Joydeep Ray, Peter L. Doyle, Subramaniam Maiyuran, Devan Burke, Philip R. Laws, ElMoustapha Ould-Ahmed-Vall, Altug Koker
  • APPARATUS AND METHOD FOR DYNAMIC PROVISIONING, QUALITY OF SERVICE, AND SCHEDULING
    Publication number: 20180293185
    Abstract: An apparatus and method for dynamic provisioning and traffic control on a memory fabric.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: BALAJI VEMBU, ALTUG KOKER, JOYDEEP RAY, ABHISHEK R. APPU, PATTABHIRAMAN K, NIRANJAN L. COORAY