Patents by Inventor Abhishek

Abhishek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10092190
    Abstract: A system for multimodal laser speckle imaging may include a first light source positioned to emit laser light toward a target, a second light source positioned to emit light toward the target, a camera positioned to receive light scattered from the target, and a processor.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: October 9, 2018
    Assignee: THE JOHNS HOPKINS UNIVERSITY
    Inventors: Abhishek Rege, Nitish Thakor, Kartikeya Murari, Nan Li
  • Patent number: 10095469
    Abstract: At least one first user and at least one second user is identified. At least one audio track is selected based on (a) the identification of the at least one first user, (b) the identification of the at least one second user, and (c) a time of day. A playback device begins playback of the selected at least one audio track.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: October 9, 2018
    Assignee: SONOS, INC.
    Inventors: Robert Reimann, David Taylor, Abhishek Kumar
  • Patent number: 10096122
    Abstract: Devices and techniques are generally described for segmentation of object image data from background image data. In some examples, the segmentation of object image data may comprise capturing image data comprising color data and depth data. In some examples, the segmentation of object image data may further include separating the depth data into a plurality of clusters of image data, wherein each cluster is associated with a respective range of depth values. In various examples, the segmentation of object image data may comprise selecting a main cluster of image data as corresponding to an object of interest in the image data. In various other examples, the segmentation of object image data may comprise identifying pixels of the main cluster that correspond to the object of interest.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 9, 2018
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Amit Kumar Agrawal, Abhishek Singh, Visesh Uday Kumar Chari, Lelin Zhang, Qiang Liu, Rohith Mysore Vijaya Kumar, David Ting-Yu Wu
  • Publication number: 20180285120
    Abstract: A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Joydeep Ray, Altug Koker, Balaji Vembu, Murali Ramadoss, Guei-Yuan Lueh, James A. Valerio, Prasoonkumar Surti, Abhishek R. Appu, Vasanth Ranganathan, Kalyan Bhairavabhatla, Arthur D. Hunter, JR., Wei-Yu Chen, Subramaniam M. Maiyuran
  • Publication number: 20180284868
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Altug Koker, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Balaji Vembu, Prasoonkumar Surti, Kamal Sinha, Eric J. Hoekstra, Wenyin Fu, Nikos Kaburlasos, Bhushan M. Borole, Travis T. Schluessler, Ankur N. Shah, Jonathan Kennedy
  • Publication number: 20180286011
    Abstract: Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to compute depth values for one or more 4×4 blocks of pixels using 16 source interpolators and 8 destination interpolators on an incoming fragment of pixel data if the destination is in min/max format, and a memory to store a depth test result performed on the one or more 4×4 blocks of pixels. Otherwise the processor is to compute depth values for one or more 8×4 blocks of pixels using 16 source interpolators and 16 destination interpolators if the destination is in plane format.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Vasanth Ranganathan, Saikat Mandal, Karol A. Szerszen, Saurabh Sharma, Vamsee Vardhan Chivukula, Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker
  • Publication number: 20180285230
    Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Nikos Kaburlasos, Balaji Vembu, Josh B. Mastronarde, Altug Koker, Eric C. Samson, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Vasanth Ranganathan, Sanjeev S. Jahagirdar
  • Publication number: 20180287855
    Abstract: Techniques for use in network incident identification are described. In response to an occurrence of an unknown network incident, a plurality of log messages (e.g. syslog messages) are received from a plurality of network components in one or more networks. In one illustrative example, a plurality of relationships between interfaces and events are derived from the received log messages and characterized as a plurality of graphical component relationships. One or more groups of connected components are determined from the graphical component relationships and network component connection data which indicate interface relationships of the network components. Here, groups of connected components may be logically joined based on the network component connection data indicating one or more interface relationships.
    Type: Application
    Filed: July 27, 2017
    Publication date: October 4, 2018
    Inventors: Guru Parthibhan Paramaguru, Prashant Anand, Vasudevan Visvanathan, Sundar Ramakrishnan, Dharmarajan Subramanian, Rohit Kumar Gupta, Abhishek Chaudhary
  • Publication number: 20180285106
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • Publication number: 20180284872
    Abstract: An embodiment may include an application processor, persistent storage media coupled to the application processor, and a graphics subsystem coupled to the application processor. The system may further include any of a performance analyzer to analyze a performance of the graphics subsystem to provide performance analysis information, a content-based depth analyzer to analyze content to provide content-based depth analysis information, a focus analyzer to analyze a focus area to provide focus analysis information, an edge analyzer to provide edge analysis information, a frame analyzer to provide frame analysis information, and/or a variance analyzer to analyze respective amounts of variance for the frame. The system may further include a workload adjuster to adjust a workload of the graphics subsystem based on the analysis information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Travis T. Schluessler, Joydeep Ray, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Kamal Sinha, James M. Holland, Pattabhiraman K., Sayan Lahiri, Radhakrishnan Venkataraman, Carson Brownlee, Vivek Tiwari, Kai Xiao, Jefferson Amstutz, Deepak S. Vembar, Ankur N. Shah, ElMoustapha Ould-Ahmed-Vall
  • Publication number: 20180284876
    Abstract: A system of reducing power consumed by a large screen display panel may comprise a display divided into a plurality of segments. A gaze tracker identifies a gaze region where a viewer(s) is looking to increase a refresh rate for segments identified in the gaze region with relation to segments outside of the gaze region. The shading rate of segments outside of the gaze region may also be lowered to save even more power.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Ya-Ti Peng, Abhishek R. Appu, Wen-Fu Kao, Sang-Hee Lee
  • Publication number: 20180286112
    Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini, Karthik Vaidyanathan, Abhishek Venkatesh, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
  • Publication number: 20180285109
    Abstract: Systems, apparatuses and methods may provide for technology that activates a first context on a graphics processor and detects a context switch condition with respect to the first context. Additionally, a second context may be activated, in response to the context switch condition, on the graphics processor while the first context is active on the graphics processor. In one example, activating the second context includes adding a group identifier to a plurality of threads corresponding to the second context and launching the plurality of threads with the group identifier on the graphics processor.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Altug Koker, Michael Apodaca, Kai Xiao, Chandrasekaran Sakthivel, Jeffery S. Boles, Adam T. Lake, Abhishek R. Appu
  • Publication number: 20180285110
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a first number of threads to be scheduled for each context of a plurality of contexts in a multi-context processing system, allocate a second number of streaming multiprocessors (SMs) to the respective plurality of contexts, and dispatch threads from the plurality of contexts only to the streaming multiprocessor(s) allocated to the respective plurality of contexts. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Altug Koker, Balaji Vembu, Abhishek R. Appu, Kamal Sinha, Prasoonkumar Surti, Kiran C. Veernapu
  • Publication number: 20180285191
    Abstract: Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Sanjeev S. Jahagirdar, Eric J. Asperheim, Subramaniam Maiyuran, Kiran C. Veernapu, Eric C. Samson, Joydeep Ray, Travis T. Schluessler, Jacek Kwiatkowski, Abhishek R. Appu, Ankur N. Shah, Altug Koker
  • Publication number: 20180285278
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, David Puffer, Prasoonkumar Surti, Lakshminarayanan Striramassarma, Vasanth Ranganathan, Kiran C. Veernapu, Balaji Vembu, Pattabhiraman K
  • Publication number: 20180286005
    Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a processing array including multiple compute blocks, each compute block including multiple processing clusters and a thread dispatch unit to dispatch threads of a workload to the multiple compute blocks based on a parallelism metric, wherein the thread dispatch unit, based on the parallelism metric, is to perform one of a first operation and a second operation, the first operation to distribute threads across the multiple compute blocks and the second operation is to concentrate threads within one of the multiple compute blocks.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Altug Koker, Balaji Vembu, Joydeep Ray, James A. Valerio, Abhishek R. Appu
  • Publication number: 20180288435
    Abstract: An embodiment of an electronic processing system may include a 2D frame which corresponds to a projection of a 360 video space, and a component predictor to predict an encode component for a first block of a 2D frame based on encode information from a neighboring block which is neighboring to the first block of the 2D frame only in the 360 video space, a prioritizer to prioritize transmission for a second block of the 2D frame based on an identified region of interest, and/or a format detector to detect a 360 video format of the 2D frame based on image content. A 360 video capture device may include a contextual tagger to tag 360 video content with contextual information which is contemporaneous with the captured 360 video content. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Jill M. Boyce, Sang-Hee Lee, Abhishek R. Appu, Wen-Fu Kao, Joydeep Ray, Ya-Ti Peng, Keith W. Rowe, Fangwen Fu, Satya N. Yedidi, Sumit Mohan, James M. Holland
  • Publication number: 20180285984
    Abstract: A method for utilizing data analytics to identify unauthorized consumption of content comprises obtaining social network activity data from one or more social networks. The obtained social network activity data is analyzed to identify one or more users involved with content associated with a content provider. A determination is made as to whether or not the one or more users are authorized to access the content based at least in part on the analysis.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Inventors: Naga A. Ayachitula, Mahesh Gajwani, Ashish Kundu, Abhishek Malvankar
  • Publication number: 20180286016
    Abstract: Systems, apparatuses and methods may provide for technology that identifies, at an image post-processor, unresolved surface data and identifies, at the image post-processor, control data associated with the unresolved surface data. Additionally, the technology may resolve, at the image post-processor, the unresolved surface data and the control data into a final image.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Applicant: Intel Corporation
    Inventors: Tomer Bar-On, Hugues Labbe, Adam T. Lake, Kai Xiao, Ankur N. Shah, Johannes Guenther, Abhishek R. Appu, Joydeep Ray, Deepak S. Vembar, ElMoustapha Ould-Ahmed-Vall