Abstract: A sputtering chamber has a target that moves with an orbital motion relative to an ion beam. An X-Y assembly allows for target movement in both the horizontal and vertical directions. The X-Y assembly has a base plate, an intermediate plate, and a target mounting plate that attaches to the target. The plates are connected together by bearing blocks that slide along rails in the X and Y directions. A rotating shaft has gears that rotate a center shaft through the base and intermediate plates. The rotating center shaft has an arm on its end that attaches to the target mounting plate. The arm produces an orbital movement of the target. Rather than simply rotating the target around the center shaft, the center of the target orbits around the center of the center shaft. Ion-beam wear is spread across the target surface, extending target life and improving deposition uniformity.

Abstract: A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself.

Abstract: A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself.

Abstract: A processor module has a cache of SRAM chips mounted on both a back and a front surface but de-coupling capacitors mounted on only the back surface. Each de-coupling capacitor is for suppressing current spikes from a pair of SRAM chips. The pair of SRAM chips includes a first SRAM chip on the same surface as the capacitor and a second SRAM chip opposite the first SRAM chip on the front surface of the module. The first SRAM chip belongs to a first bank while the second SRAM chip belongs to a second bank. Two chip-enable signals control access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one SRAM chip in the pair of SRAM chips creates a current spike at any time. Thus, a capacitor can be shared between the two SRAM chips in the pair. The shared capacitor can be mounted next to or under one of the SRAM chips, or formed within the multi-layer substrate itself.

Abstract: A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself.

Abstract: A circuit board fabrication apparatus and method having a vibratory feeder tray is disclosed. The feeder tray is preferably of low mass and horizontally-disposed and has multiple grooves which closely fit electronic parts, and hollowed-out bottom portions, generally below the rails separating the grooves. The hollow portions significantly contribute to low mass. Almost 50% of the mass of the tray's top plate may be removed. The parts are picked up one at a time and placed at precise positions on circuit board substrates by the rotating nozzles of a pick-and-place turret. An electromagnetic coil operating below the grooves of the feeder tray smoothly and continuously advances the parts in the grooves to the region in which they are picked up by the nozzles. Additionally, a slider table supporting the vibratory feeder tray positions each groove of the feeder tray in turn at the uptake point of the turret.

Abstract: A container for memory modules comprising a generally rectangular shape with a lid and tray with a multitude of finger-like protrusions forming vertical slots therebetween for receiving memory modules. The interior is formed such that a cavity may be created above and below the memory modules contained inside providing a buffer region, which protects the contents from damage when the exterior of the container is subjected to physical contact.

Abstract: An add-on card which has a flat surface on the top side on which a plastic quad flat pack integrated circuit packaged integrated circuit can be soldered upon. The other side of the add-on card has downwardly protruding pins that can plug into a pin grid array integrated circuit socket. A method of manufacturing a add-on card whereby bonding pads are disposed on one side of the add-on card and pins are disposed on the other side of the add-on card.

Abstract: A container for memory modules comprising a generally rectangular shape with a lid and tray with a multitude of finger-like protrusions forming vertical slots therebetween for receiving memory modules. The interior is formed such that a cavity may be created above and below the memory modules contained inside providing a buffer region, which protects the contents from damage when the exterior of the container is subjected to physical contact.

Abstract: An add-on card which has a flat surface on the top side on which a plastic quad flat pack integrated circuit packaged integrated circuit can be soldered upon. The other side of the add-on card has downwardly protruding pins that can plug into a pin grid array integrated circuit socket. A method of manufacturing a add-on card whereby bonding pads are disposed on one side of the add-on card and pins are disposed on the other side of the add-on card.