Abstract: A portable universal serial bus (USB) data exchanger device is described herein. In one embodiment, the portable USB data exchanger includes at least one flash memory chip having a multi-level cell (MLC) memory array, a flash memory controller coupled to the at least one flash memory chip, the flash memory controller having a USB on-the-go (OTG) capability and controlling reading and writing of the flash memory chip, a first extended USB (EUSB) connector coupled to the flash memory controller to be coupled to a host, and a second EUSB connector coupled to the flash memory controller to be coupled to a slave USB device. The Portable USB data exchanger can communicate with either a host or a slave USB device without polling. Other methods and apparatuses are also described.

Abstract: An electronic data flash card is accessible by a host computer, and includes a processing unit connected to a flash memory device that stores a data file, and an input-output interface circuit activated so as to establish a communication with the host computer. In an embodiment, the electronic data flash card uses a USB input/output interface circuit for communication with the host computer. A flash memory controller includes an index for converting logical addresses sent by the host computer into physical addresses associated with sectors of the flash memory device. The index is controlled by arbitration logic referencing to values from various look up tables and valid data stored in the flash memory device. The flash memory controller further includes a first-in-first-out unit (FIFO) for recycling obsolete sectors of the flash memory device in the background process so that they are available for reprogramming.

Abstract: An extended universal-serial bus (EUSB) bridge to a host computer can have peripheral component interconnect express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.

Abstract: A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.

Abstract: An open-frame flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips, a controller chip, and a Serial AT-Attachment (SATA) connector soldered to it. The PCBA is only partially encased by left and right frames or by a U-shaped bracket frame. The frames have PCBA supports and guide posts that fit near edges of the PCBA. The frames do not cover the top and bottom of the PCBA, allowing chips on the PCBA to be ventilated by unblocked air flow. Screws that attach the PCBA to the frame have metal collars that ground the frame to the PCBA's ground plane. The screws form a current path to draw any electro-static-discharge (ESD) current off the frame and onto a PCBA ground. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the open frame.

Abstract: A flash-memory drive replaces a hard-disk drive using an integrated device electronics (IDE) interface. The flash drive has a printed-circuit board assembly (PCBA) with a circuit board with flash-memory chips and a controller chip. The controller chip includes an input/output interface circuit to an external computer over the IDE interface, and a processing unit to read blocks of data from the flash-memory chips. The PCBA is encased inside an upper case and a lower case, with an IDE connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Center lines formed on the inside of the cases fit between rows of flash-memory chips to improve case rigidity. The connector has two rows of pins that straddle the center line of the circuit board for a balanced design.

Abstract: A memory module assembly includes two-plate heat sink attached to one or more of the integrated circuits (e.g., memory devices) of a memory module PCBA by adhesive. The adhesive is either heat-activated or heat-cured. The adhesive is applied to either the memory devices or the heat-sink plates, and then compressed between the heat-sink plates and memory module using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. The two heat sink plates are then secured by a clip to form a rigid frame.

Abstract: Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time depends on the write data state and is relatively long for set, but short for clear. A PCM chip has a lookup table (LUT) caching write data that is later written to a PCM bank. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the slower PCM. The PCM chip has upstream and downstream serial interfaces to other PCM chips arranged as a token stub. Requests are passed down the token-stub while acknowledgements are passed up the token-stub to the host's memory controller. Shared chip-enable lines are driven by the upstream PCM chip for requests, and by the downstream PCM chip for acknowledgements.

Abstract: A USB device including a bistable mechanism that serves to bias a plug connector into one of two stable states, where the first stable state is associated with a retracted position in which the plug connector is fully retracted inside a housing, and the second stable state is associated with a deployed position in which the plug connector extends through the front opening for coupling to a host system. Movement of the plug connector form the retracted to the deployed position is performed by manually applying a force to a handle portion that protrudes through a slot defined in the housing. The bistable mechanism resists the deploying force until an equilibrium point is reach, after which the bistable mechanism releases stored potential energy to complete the deploying process and to maintain the plug connector is the deployed position.

Abstract: A portable USB device with an improved configuration is described herein. According to one embodiment, a portable USB device includes a core unit having a USB plug connector coupled to one or more multi-level cell (MLC) flash memory devices and an MLC flash controller disposed therein. The portable USB device further includes a housing for enclosing the core unit, including a front end opening to allow the USB plug connector to be deployed. The portable USB device further includes a core unit carrier for carrying the core unit for deploying and retracting the core unit, including a slide button to allow a finger of a user to slide the USB plug connector of the core unit in and out of the housing via the front end opening of the housing.

Abstract: A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.

Abstract: An electronic device includes multiple IC dies stacked in an offset stacking arrangement on a substrate. Each IC die includes electrically isolated step pads that facilitates transmitting a dedicated signal between a (beginning) substrate bonding pad and a selected (terminal) contact pad of any die by way of short bonding wires that extend up the stack between the electrically isolated step pads. A memory devices includes stacked memory IC die, wherein “shared” signal transmission paths are formed by associated bonding wires that link corresponding contact pads of each memory die, and dedicated select/control signals are transmitted to each memory die by separate transmission paths formed in part by associated electrically isolated step pads. Substrate space overhung by the stack is used for passive components and IC dies. Memory controller die may be mounted on the stack and connected by dedicated transmission paths utilizing the electrically isolated step pads.

Abstract: A USB device including a housing and a rear cap that is rotatably connected to the housing to facilitate deploying and retracting a plug connector through a front opening of the housing. The plug connector is fixedly connected onto the front end of a sliding rack assembly that is disposed in housing such that the sliding rack assembly is slidable along a longitudinal axis. The sliding rack assembly includes a carrier including a carrier tray for supporting electronic devices and an elongated positioning rod extending from a rear portion of the carrier tray. The positioning rod is operably engaged with an actuator portion such that manual rotation of the rear cap relative to the housing around the longitudinal axis causes the sliding rack assembly to slide inside the housing between retracted and deployed positions.

Abstract: A memory module assembly includes two-plate heat sink attached to one or more of the integrated circuits (e.g., memory devices) of a memory module PCBA by adhesive. The adhesive is either heat-activated or heat-cured. The adhesive is applied to either the memory devices or the heat-sink plates, and then compressed between the heat-sink plates and memory module using a fixture. The fixture is then passed through an oven to activate/cure the adhesive. The two heat sink plates are then secured by a clip to form a rigid frame.

Abstract: A USB device including a housing and a protective cap that are slidably and/or pivotably connected together such that the protective cap is able to slide and/or pivot between an open position, in which a plug connector extending from the front of the housing is exposed for operable coupling to a host system, and a closed position, in which the protective cap is disposed over the front end portion of the housing to protect the plug connector. A pivoting/sliding mechanism is provided on the housing and cap that secures the protective cap to the housing at all times, including during transitional movements of the protective cap between the opened and closed positions.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers.

Abstract: A case-grounded flash-memory drive has a printed-circuit board assembly (PCBA) with flash-memory chips and a controller chip. The PCBA is encased inside an upper case and a lower case, with a Serial AT-Attachment (SATA) connector that fits through and opening between the cases. The cases can be assembled with the PCBA by a snap-together, ultrasonic-press, screw-fastener, or thermal-bond adhesive method. Dual-axis case-grounding pins draw any electro-static-discharges (ESD) current off the upper case along a primary axis and onto a PCBA ground through a secondary axis washer that is screwed into the PCBA. The primary axis body of the dual-axis case-grounding pins fits around a PCBA notch while the secondary axis passes through a metalized alignment hole for grounding. When the SATA connector is inserted into a host, the host ground sinks ESD currents collected by the dual-axis case-grounding pins.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline.