Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of layers of neurons interposed with layers of synapses. A set of crossbar arrays of memristive devices, connected between row and column lines, implements the layers of synapses. Each memristive device stores a weight for a synapse interconnecting a respective pair of neurons in successive neuron layers. The training method includes performing forward propagation, backpropagation and weight-update operations of an iterative training scheme by applying input signals, associated with respective neurons, to row or column lines of the set of arrays to obtain output signals on the other of the row or column lines, and storing digital signal values corresponding to the input and output signals. The weight-update operation is performed by calculating digital weight-correction values for respective memristive devices, and applying programming signals to those devices to update the stored weights.

Abstract: A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Abstract: A memristor memory device comprises a memristive memory cell, an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal are directly attached to the memristive memory cell, and the gate terminal is electrically isolated from the memristive memory cell. The gate terminal is configured for receiving an electrical signal for a volatile modulation of a conductance of the memristive memory cell, by which a correction of non-ideal conductance modulations of the memristor memory device is achieved.

Abstract: A neuromorphic memory element comprises a memristor, a plurality of the neuromorphic memory elements and a method for operating the same may be provided. The memristor comprises an input signal terminal, an output signal terminal, and a control signal terminal, and a memristive active channel comprising a phase change material. The memristive active channel extends longitudinal between the input signal terminal and the output signal terminal, and a control signal voltage at the control signal terminal is configured to represent volatile biological neural processes of the neuromorphic memory element, and a bias voltage between the input signal terminal and the output signal terminal is configured to represent non-volatile biological neural processes of the neuromorphic memory element.

Abstract: The exemplary embodiments disclose a method, a computer program product, and a computer system for a gated recurrent neural network (RNN). The exemplary embodiments may include providing an element processor, providing a distinct memory array for a respective set of one or more elements of a hidden state vector, storing in the memory array a group of columns of weight matrices that enable a computation of the set of one or more elements, computing one or more elements of each of multiple activation vectors using a set of one or more columns of the group of columns associated with each of the multiple activation vectors, and performing by the element processor an elementwise gating operation on computed elements, resulting in the set of one or more elements.

Abstract: Neuromorphic synapse apparatus is provided comprising a synaptic device and a control signal generator. The synaptic device comprises a memory element, disposed between first and second terminals, for conducting a signal between those terminals with an efficacy which corresponds to a synaptic weight in a read mode of operation, and a third terminal operatively coupled to the memory element. The memory element has a non-volatile characteristic, which is programmable to vary the efficacy in response to programming signals applied via the first and second terminals in a write mode of operation, and a volatile characteristic which is controllable to vary the efficacy in response to control signals applied to the third terminal. The control signal generator is responsive to input signals and is adapted to apply control signals to the third terminal in the read and write modes, in dependence on the input signals, to implement predetermined synaptic dynamics.

Abstract: A circuit implementing a spiking neural network that includes a learning component that can learn from temporal correlations in the spikes regardless of correlations in the rates. In some embodiments, the learning component comprises a rate-discounting component. In some embodiments, the learning rule computes a rate-normalized covariance (normcov) matrix, detects clusters in this matrix, and sets the synaptic weights according to these clusters. In some embodiments, a synapse with a long-term plasticity rule has an efficacy that is composed by a weight and a fatiguing component. In some embodiments, A Hebbian plasticity component modifies the weight component and a short-term fatigue plasticity component modifies the fatiguing component. The fatigue component increases with increases in the presynaptic spike rate. In some embodiments, the fatigue component increases are implemented in a spike-based manner.

Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Abstract: The present disclosure relates to a method for executing a computation task composed of at least one set of operations where subsets of pipelineable operations of the set of operations are determined in accordance with a pipelining scheme. A single routine may be created for enabling execution of the determined subsets of operations by a hardware accelerator. The routine has, as arguments, a value indicative of input data and values of configuration parameters of the computation task, where a call of the routine causes a scheduling of the subsets of operations on the hardware accelerator in accordance with the values of the configuration parameters. Upon receiving input data of the computation task, the routine may be called to cause the hardware accelerator to perform by the computation task in accordance with the scheduling.

Abstract: A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Abstract: The invention is directed to a device for high-dimensional encoding of a plurality of sequences of quantitative data signals. The device comprises a plurality of input channels for receiving the plurality of sequences of quantitative data signals and an encoding unit. The encoding unit is configured to perform a temporal high-dimensional encoding of n-grams of the plurality of sequences of quantitative data signals; thereby creating a plurality of temporally encoded hypervectors for the plurality of input channels. The encoding unit is further configured to perform a spatial high-dimensional encoding of the plurality of temporally encoded hypervectors, thereby creating a temporally and spatially encoded hypervector. The device further comprises a configuration controller. The configuration controller is adapted to configure the high-dimensional encoding in dependence on one or more hyperparameter values.

Abstract: A circuit implementing a spiking neural network that includes a learning component that can learn from temporal correlations in the spikes regardless of correlations in the rates. In some embodiments, the learning component comprises a rate-discounting component. In some embodiments, the learning rule computes a rate-normalized covariance (normcov) matrix, detects clusters in this matrix, and sets the synaptic weights according to these clusters. In some embodiments, a synapse with a long-term plasticity rule has an efficacy that is composed by a weight and a fatiguing component. In some embodiments, A Hebbian plasticity component modifies the weight component and a short-term fatigue plasticity component modifies the fatiguing component. The fatigue component increases with increases in the presynaptic spike rate. In some embodiments, the fatigue component increases are implemented in a spike-based manner.

Abstract: The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.

Abstract: The invention is directed a device for high-dimensional encoding of a plurality of sequences of quantitative data signals. The device comprises a memory crossbar array comprising a plurality of resistive devices, a first peripheral circuit connected to the memory crossbar array, and a second peripheral circuit connected to the first peripheral circuit. The device is configured to receive the plurality of sequences of quantitative data signals via a plurality of input channels and to store elements of a plurality of precomputed basis hypervectors as conductance states of the resistive devices. The plurality of basis hypervectors are bound to respective input channels. The first peripheral circuit performs a temporal encoding of n-grams of the quantitative data signals thereby creating a plurality of temporally encoded hypervectors. The second peripheral circuit performs a spatial encoding of the plurality of temporally encoded hypervectors. This creates a temporally and spatially encoded hypervector.

Abstract: A co-processor for performing a matrix multiplication of an input matrix with a data matrix in one step may be provided. The co-processor receives input signals for the input matrix as optical signals. A plurality of photonic memory elements is arranged at crossing points of an optical waveguide crossbar array. The plurality of memory elements is configured to store values of the data matrix. Input signals are connected to input lines of the optical waveguide crossbar array. Output lines of the optical waveguide crossbar array represent a dot-product between a respective column of the optical waveguide crossbar array and the received input signals, and values of elements of the input matrix to be multiplied with the data matrix correspond to light intensities received at input lines of the respective photonic memory elements. Additionally, different wavelengths are used for each column of the input matrix optical signals.

Abstract: Methods and apparatus are provided for implementing propagation of probability distributions of random variables over a factor graph. Such a method includes providing a spiking neural network, having variable nodes interconnected with factor nodes, corresponding to the factor graph. Each of the nodes comprises a set of neurons configured to implement computational functionality of that node. The method further comprises generating, for each of a set of the random variables, at least one spike signal in which the probability of a possible value of that variable is encoded via the occurrence of spikes in the spike signal, and supplying the spike signals for the set of random variables as inputs to the neural network at respective variable nodes. The probability distributions are propagated via the occurrence of spikes in signals propagated through the neural network.

Abstract: A computer-implemented method of mixed-precision deep learning with multi-memristive synapses may be provided. The method comprises representing, each synapse of an artificial neural network by a combination of a plurality of memristive devices, wherein each of the plurality of memristive devices of each of the synapses contributes to an overall synaptic weight with a related device significance, accumulating a weight gradient ?W for each synapse in a high-precision variable, and performing a weight update to one of the synapses using an arbitration scheme for selecting a respective memristive device, according to which a threshold value related to the high-precision variable for performing the weight update is set according to the device significance of the respective memristive device selected by the arbitration schema.

Abstract: A computer-implemented method for classification of an input element to an output class in a spiking neural network may be provided. The method comprises receiving an input data set comprising a plurality of elements, identifying a set of features and corresponding feature values for each element of the input data set, and associating each feature to a subset of spiking neurons of a set of input spiking neurons of the spiking neural network. Furthermore, the method comprises also generating, by the input spiking neurons, spikes at pseudo-random time instants depending on a value of the feature for a given input element, and classifying an element into a class depending on a distance measure value between output spiking patterns at output spiking neurons of the spiking neural network and a predefined target pattern related to the class.

Abstract: A method of operating a neuromorphic system is provided. The method includes applying voltage signals across input lines of a crossbar array structure, the crossbar array structure including rows and columns interconnected at junctions via programmable electronic devices, the rows including the input lines for applying voltage signals across the electronic devices and the columns including output lines for outputting currents. The method also includes correcting, via a correction unit connected to the output lines, each of the output currents obtained at the output lines according to an affine transformation to compensate for temporal conductance variations in the electronic devices.