Abstract: The present disclosure relates to a method for implementing processing elements in a chip card such that the processing elements can communicate data between each other in order to perform a computation task, wherein the data communication requires each processing element to have a respective number of connections to other processing elements. The method comprises: providing a complete graph with an even number of nodes that is higher than the maximum of the numbers of connections by one or two. If the number of processing elements is higher that the number of nodes of the graph, the graph may be duplicated and the duplicated graphs may be combined into a combined graph. A methodology for placing and connecting the processing elements may be determined in accordance with the structure of nodes of a resulting graph, the resulting graph being the complete graph or the combined graph.

Abstract: A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

Abstract: Methods are provided for training weights of an artificial neural network to be implemented by inference computing apparatus in which the trained weights are stored as programmed conductance states of respective predetermined memristive devices. Such a method includes deriving for the memristive devices a probability distribution indicating distribution of conductance errors for the devices in the programmed conductance states. The method further comprises, in a digital computing apparatus: training the weights via an iterative training process in which the weights are repeatedly updated in response to processing by the network of training data which is propagated over the network via the weights; and applying noise dependent on said probability distribution to weights used in the iterative training process.

Abstract: Methods and apparatus are provided for training an artificial neural network, having a succession of neuron layers with interposed synaptic layers each storing a respective set of weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for at least one of the synaptic layers, providing a plurality P1 of arrays of memristive devices, each array storing the set of weights of that synaptic layer S1 in respective memristive devices, and, in a signal propagation operation, supplying respective subsets of the signals to be weighted by the synaptic layer S1 in parallel to the P1 arrays. The method also includes, in a weight-update calculation operation, calculating updates to respective weights stored in each of the P1 arrays in dependence on signals propagated by the neuron layers.

Abstract: A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.

Abstract: A device performs a matrix-vector multiplication of a matrix with a vector. The device includes a crossbar array having row lines, column lines and junctions arranged between the row lines and the column lines. Each junction includes a programmable resistive element and an access element for accessing the programmable resistive element. The device further includes a signal generator configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication. The device further includes a readout circuit and control circuitry configured to control the signal generator and the readout circuit. The readout circuit is configured to apply read voltages having a positive voltage sign and negative read voltages having a negative voltage sign to the row lines of the crossbar array. The readout circuit is further configured to read out column currents of the plurality of column lines of the crossbar array.

Abstract: A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.

Abstract: A memory device may include a plurality of resistive elements and a control unit for controlling the memory device. The memory device is configured to program single weights of the memory device by groups of at least two resistive elements. A related method and a related computer program product may be also provided.

Abstract: The present disclosure relates to a method of generating spikes by a neuron of a spiking neural network. The method comprises generating at each time, wherein the spike generation encodes at each time instant at least two variable values at the neuron. Synaptic weights may be optimized for a spike train generated by a given presynaptic neuron of a spiking neural network, wherein the spike train being indicative of features of at least one timescale.

Abstract: A device for performing a multiplication of a matrix with a vector. The device comprises a plurality of memory elements, a signal generator and a readout circuit. The signal generator is configured to apply programming signals to the memory elements. The signal generator is further configured to control a first signal parameter of the programming signals in dependence on matrix elements of the matrix and to control a second signal parameter of the programming signals in dependence on vector elements of the vector. The readout circuit is configured to read out memory values of the memory elements. The memory values represent result values of vector elements of a product vector of the multiplication. The memory elements may be in particular resistive memory elements or photonic memory elements. Additionally there is provided a related method and design structure for performing the multiplication of a matrix with a vector.

Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.

Abstract: A computer-implemented method of mixed-precision deep learning with multi-memristive synapses may be provided. The method comprises representing, each synapse of an artificial neural network by a combination of a plurality of memristive devices, wherein each of the plurality of memristive devices of each of the synapses contributes to an overall synaptic weight with a related device significance, accumulating a weight gradient ?W for each synapse in a high-precision variable, and performing a weight update to one of the synapses using an arbitration scheme for selecting a respective memristive device, according to which a threshold value related to the high-precision variable for performing the weight update is set according to the device significance of the respective memristive device selected by the arbitration schema.

Abstract: A multiplication device for performing a matrix-vector-multiplication may be provided. The multiplication device comprises a memristive crossbar array comprising a plurality of memristive devices. The device comprises a decomposition unit adapted for decomposing a matrix into a partial sum of multiple sub-matrices, and decomposing a vector into a sum of multiple sub-vectors, a programming unit adapted for programming the plurality of the memristive devices with values representing elements of the sub-matrices such that each one of the memristive devices corresponds to one of the elements of the sub-matrices, an applying unit adapted for applying elements of one of the multiple sub-vectors as input values to the memristive crossbar array to input lines of the memristive crossbar array resulting in partial results at output lines of the memristive crossbar array, and a summing unit adapted for scaling and summing the partial results building the product of the matrix and the vector.

Abstract: The invention is directed to a resistive memory device comprising a control unit for controlling a memory cell of the memory device. The memory cell includes a first terminal, a second terminal and a phase change segment comprising a phase-change material. The phase change segment is arranged between the first terminal and the second terminal. The phase change material is antimony. The phase change segment retains an amorphous region during a write operation. The control unit, during the write operation, applies an electrical programming pulse to the terminals to cause a portion of the phase change segment to transition from a crystalline phase to an amorphous phase comprising the amorphous region. A trailing edge duration of the electrical programming pulse is adjusted based on ambient temperature to prevent re-crystallization of the amorphous region. Shorter trailing edge durations are used at increasing ambient temperatures.

Abstract: Embodiments of the invention are directed to a method to modify material properties of a functional material of a nanoscale device post-fabrication. The method includes performing one or more conditioning steps. The conditioning steps include applying electrical conditioning signals of predefined form to the nanoscale device, thereby performing an in-situ heating of the functional material and inducing thermally a displacement of atoms, molecules or ions of the functional material of the nanoscale device. Embodiments of the invention further concerns a related electronic device.

Abstract: Methods and apparatus are provided for implementing propagation of probability distributions of random variables over a factor graph. Such a method includes providing a spiking neural network, having variable nodes interconnected with factor nodes, corresponding to the factor graph. Each of the nodes comprises a set of neurons configured to implement computational functionality of that node. The method further comprises generating, for each of a set of the random variables, at least one spike signal in which the probability of a possible value of that variable is encoded via the occurrence of spikes in the spike signal, and supplying the spike signals for the set of random variables as inputs to the neural network at respective variable nodes. The probability distributions are propagated via the occurrence of spikes in signals propagated through the neural network.

Abstract: A sensor arrangement for position sensing comprises a row of multiple magnetoresistive elements. A magnetic field source (3) provides a magnetic field with a first magnetic pole (N) and a second magnetic pole (S). The magnetic field source (3) is arranged such that magnetoresistive elements of the row face one of: the first magnetic pole (N) or second magnetic pole (S). The first magnetoresistive element is arranged in the magnetic field and provides a first output signal dependent on a position of the magnetoresistive element relative to the magnetic field source (3). A measurement unit is configured to determine a position of the magnetic field source (3) relative to the magnetoresistive elements of the row dependent on the first output signals of the magnetoresistive elements.

Abstract: A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.

Abstract: A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.

Abstract: A computer-implemented method for managing datasets of a storage system is provided, wherein the datasets have respective sets of metadata, the method including: successively feeding first sets of metadata to a spiking neural network (SNN), the first sets of metadata fed corresponding to datasets of the storage system that are labeled with respect to classes they belong to, so as to be associated with class labels, for the SNN to learn representations of said classes in terms of connection weights that weight the metadata fed; successively feeding second sets of metadata to the SNN, the second sets of metadata corresponding to unlabeled datasets of the storage system, for the SNN to infer class labels for the unlabeled datasets, based on the second sets of metadata fed and the representations learned; and managing datasets in the storage system, based on class labels of the datasets, these including the inferred class labels.