Patents by Inventor Adel A. Elsherbini

Adel A. Elsherbini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149500
    Abstract: Microelectronic assemblies that include a lithographically-defined substrate integrated waveguide (SIW) component, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate portion having a first face and an opposing second face; and an SIW component that may include a first conductive layer on the first face of the package substrate portion, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and a first conductive sidewall and an opposing second conductive sidewall in the dielectric layer, wherein the first and second conductive sidewalls are continuous structures.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini
  • Publication number: 20220149036
    Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Patent number: 11329359
    Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Adel A. Elsherbini, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan
  • Patent number: 11329358
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto
  • Publication number: 20220140085
    Abstract: Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Applicant: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, Nicole K. Thomas, Hubert C. George, James S. Clarke, Adel A. Elsherbini
  • Patent number: 11309619
    Abstract: A waveguide coupling system may include at least one waveguide member retention structure disposed on an exterior surface of a semiconductor package. The waveguide member retention structure may be disposed a defined distance or at a defined location with respect to an antenna carried by the semiconductor package. The waveguide member retention structure may engage and guide a waveguide member slidably inserted into the respective waveguide member retention structure. The waveguide member retention structure may position the waveguide member at a defined location with respect to the antenna to maximize the power transfer from the antenna to the waveguide member.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Sasha Oster, Georgios Dogiamis, Telesphor Kamgaing, Adel Elsherbini, Shawna Liff, Aleksandar Aleksov, Johanna Swan
  • Patent number: 11302599
    Abstract: A heat dissipation device may be formed as a thermally conductive structure having at least one thermal isolation structure extending at least partially through the thermally conductive structure. The heat dissipation device may be thermally connected to a plurality of integrated circuit devices, such that the at least one thermal isolation structure is positioned between at least two integrated circuit devices. The heat dissipation device allows for heat transfer away from each of the plurality of integrated circuit devices, such as in a z-direction within the thermally conductive structure, while substantially preventing heat transfer in either the x-direction and/or the y-direction within the thermally isolation structure, such that thermal cross-talk between integrated circuit devices is reduced.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Adel Elsherbini, Johanna Swan
  • Patent number: 11296040
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Patent number: 11296052
    Abstract: A device package has substrates disposed on top of one another to form a stack, and pads formed on at least one of the top surface and the bottom surface of each of the substrates. The device package has interconnects electrically coupling at least one of the top surface and the bottom surface of each substrate to at least one of the top surface and the bottom surface of another substrate. The device package has pillars disposed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates. The device package also has adhesive layers formed between at least one of the top surface and the bottom surface of one or more substrates to at least one of the top surface and the bottom surface of other substrates.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Preston T. Meyers, Javier A. Falcon, Shawna M. Liff, Joe R. Saucedo, Adel A. Elsherbini, Albert S. Lopez, Johanna M. Swan
  • Publication number: 20220102339
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Pratik KOIRALA, Nicole K. THOMAS, Paul B. FISCHER, Adel A. ELSHERBINI, Tushar TALUKDAR, Johanna M. SWAN, Wilfred GOMES, Robert S. CHAU, Beomseok CHOI
  • Publication number: 20220102261
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 31, 2022
    Inventors: Adel A. ELSHERBINI, Mathew J. MANUSHAROW, Krishna BHARATH, William J. LAMBERT, Robert L. SANKMAN, Aleksandar ALEKSOV, Brandon M. RAWLINGS, Feras EID, Javier SOTO GONZALEZ, Meizi JIAO, Suddhasattwa NAD, Telesphor KAMGAING
  • Publication number: 20220102344
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Pratik KOIRALA, Nicole K. THOMAS, Paul B. FISCHER, Adel A. ELSHERBINI, Tushar TALUKDAR, Johanna M. SWAN, Wilfred GOMES, Robert S. CHAU, Beomseok CHOI
  • Publication number: 20220102270
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Patent number: 11289431
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Publication number: 20220093517
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid, Randy B. Osborne, Van H. Le
  • Publication number: 20220093561
    Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Feras Eid, Adel A. Elsherbini, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20220093725
    Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Mohammad Enamul Kabir, Zhiguo Qian, Gerald S. Pasdast, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Aleksandar Aleksov, Feras Eid
  • Publication number: 20220093546
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff
  • Publication number: 20220093492
    Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Han Wui Then, Kimin Jun, Aleksandar Aleksov, Mohammad Enamul Kabir, Shawna M. Liff, Johanna M. Swan, Feras Eid
  • Publication number: 20220093531
    Abstract: A switch in a package substrate of a microelectronic package is provided, the switch comprising: an actuator plate; a strike plate; and a connecting element mechanically coupling the actuator plate and the strike plate. The switch is configured to move within a cavity inside the package substrate between an open position and a closed position, a conductive material is coupled to the switch and to a ground via in the package substrate, and the conductive material is configured to move with the switch, such that the switch is conductively coupled to the ground via in the open position and the closed position.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan