Patents by Inventor Adel A. Elsherbini
Adel A. Elsherbini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061194Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include an interconnect die in a first layer surrounded by a dielectric material; a processor integrated circuit (processor IC) and an integrated circuit (IC) in a second layer, the second layer on the first layer, wherein the interconnect die is electrically coupled to the processor IC and the IC by first interconnects having a pitch of less than 10 microns between adjacent first interconnects; a photonic integrated circuit (PIC) and a substrate in a third layer, the third layer on the second layer, wherein the PIC has an active surface, and wherein the active surface of the PIC is coupled to the IC by second interconnects having a pitch of less than 10 microns between adjacent second interconnects; and a fiber connector optically coupled to the active surface of the PIC.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, David Hui, Haris Khan Niazi, Wenhao Li, Bhaskar Jyoti Krishnatreya, Henning Braunisch, Shawna M. Liff, Jiraporn Seangatith, Johanna M. Swan, Krishna Vasanth Valavala, Xavier Francois Brun, Feras Eid
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Publication number: 20240063143Abstract: Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Lance C. Hibbeler, Omkar Karhade, Chytra Pawashe, Kimin Jun, Feras Eid, Shawna Liff, Mohammad Enamul Kabir, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Wenhao Li
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Publication number: 20240063132Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Scott E. Siers, Gerald S. Pasdast, Johanna M. Swan, Henning Braunisch, Kimin Jun, Jiraporn Seangatith, Shawna M. Liff, Mohammad Enamul Kabir, Sathya Narasimman Tiagaraj
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Publication number: 20240063147Abstract: Techniques and mechanisms to mitigate corrosion to via structures of a composite chiplet. In an embodiment, a composite chiplet comprises multiple integrated circuit (IC) components which are each in a different respective one of multiple levels. One or more conductive vias extend through an insulator layer in a first level of the multiple levels. An annular structure of the composite chiplet extends vertically through the insulator layer, and surrounds the one or more conductive vias in the insulator layer. The annular structure mitigates an exposure of the one or more conductive vias to moisture which is in a region of the insulator layer that is not surrounded by the annular structure. In another embodiment, the annular structure further surrounds an IC component which extends in the insulator layer.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Mohammad Enamul Kabir, Johanna Swan, Omkar Karhade, Kimin Jun, Feras Eid, Shawna Liff, Xavier Brun, Bhaskar Jyoti Krishnatreya, Tushar Talukdar, Haris Khan Niazi
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Publication number: 20240063183Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Anne Augustine, Beomseok Choi, Kimin Jun, Omkar G. Karhade, Shawna M. Liff, Julien Sebot, Johanna M. Swan, Krishna Vasanth Valavala
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Publication number: 20240063091Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel Elsherbini, Feras Eid, Scot Kellar, Yoshihiro Tomita, Rajiv Mongia, Kimin Jun, Shawna Liff, Wenhao Li, Johanna Swan, Bhaskar Jyoti Krishnatreya, Debendra Mallik, Krishna Vasanth Valavala, Lei Jiang, Xavier Brun, Mohammad Enamul Kabir, Haris Khan Niazi, Jiraporn Seangatith, Thomas Sounart
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Patent number: 11908802Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 16, 2022Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
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Patent number: 11901330Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.Type: GrantFiled: December 21, 2022Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
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Patent number: 11895815Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.Type: GrantFiled: June 23, 2020Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Georgios Dogiamis, Adel Elsherbini, Feras Eid
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Patent number: 11887946Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.Type: GrantFiled: September 30, 2022Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Telesphor Kamgaing, Adel A. Elsherbini, Sasha N. Oster
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Patent number: 11887944Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.Type: GrantFiled: June 23, 2020Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Georgios Dogiamis, Feras Eid, Adel Elsherbini
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Patent number: 11881457Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.Type: GrantFiled: March 4, 2021Date of Patent: January 23, 2024Assignee: Tahoe Research, Ltd.Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Henning Braunisch, Krishna Bharath, Javier Soto Gonzalez, Javier A. Falcon
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Publication number: 20240021534Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.Type: ApplicationFiled: September 28, 2023Publication date: January 18, 2024Applicant: Intel CorporationInventors: Shawna M. LIFF, Adel A. ELSHERBINI, Johanna M. SWAN
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Patent number: 11842826Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.Type: GrantFiled: June 23, 2020Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Adel Elsherbini, Feras Eid, Johanna Swan, Georgios Dogiamis
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Patent number: 11830831Abstract: Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.Type: GrantFiled: September 23, 2016Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Georgios Dogiamis, Sasha Oster, Johanna Swan, Shawna Liff, Adel Elsherbini, Telesphor Kamgaing, Aleksandar Aleksov
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Patent number: 11823972Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.Type: GrantFiled: July 20, 2018Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Feras Eid, Adel Elsherbini, Johanna Swan
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Publication number: 20230369236Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Applicant: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Publication number: 20230343716Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Applicant: Intel CorporationInventors: Adel A. ELSHERBINI, Amr ELSHAZLY, Arun CHANDRASEKHAR, Shawna M. LIFF, Johanna M. SWAN
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Patent number: 11791277Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.Type: GrantFiled: April 8, 2022Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan
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Patent number: 11791528Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.Type: GrantFiled: April 6, 2022Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto