Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.

Abstract: Embodiments may relate an electronic device that includes a first server blade and a second server blade coupled with a chassis. The first and second server blades may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first and second server blades such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a transmitter/receiver logic (TRL) die coupled to the first surface of the package substrate; a plurality of antenna elements adjacent the second surface of the package substrate; and a transmitter/receiver chain (TRC) die, wherein the TRC die is embedded in the package substrate, and wherein the TRC die is electrically coupled to the RF die and at least one of the plurality of antenna elements via conductive pathways in the package substrate. In some embodiments, a microelectronic assembly may further include a double-sided TRC die. In some embodiments, a microelectronic assembly may further include a TRC die having an amplifier. In some embodiments, a microelectronic assembly may further include a TRL die having a modem and a phase shifter.

Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a photonic receiver; and a die coupled to the photonic receiver by interconnects, wherein the die includes a device layer between a first interconnect layer of the die and a second interconnect layer of the die. In still some embodiments, a microelectronic assembly may include a photonic transmitter; and a die coupled to the photonic transmitter by interconnects, wherein the die includes a device layer between a first interconnect layer of the die and a second interconnect layer of the die.

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

Abstract: Embodiments may relate to a microelectronic package comprising: a die and a package substrate coupled to the die with a first interconnect on a first face. The package substrate comprises: a second interconnect and a third interconnect on a second face opposite to the first face; a conductive signal path between the first interconnect and the second interconnect; a conductive ground path between the second interconnect and the third interconnect; and an electrostatic discharge (ESD) protection material coupled to the conductive ground path. The ESD protection material comprises a first electrically-conductive carbon allotrope having a first functional group, a second electrically-conductive carbon allotrope having a second functional group, and an electrically-conductive polymer chemically bonded to the first functional group and the second functional group permitting an electrical signal to pass between the first and second electrically-conductive carbon allotropes.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

Abstract: Embodiments may relate to a microelectronic package that includes a substrate signal path and a waveguide. The package may further include dies that are communicatively coupled with one another by the substrate signal path and the waveguide. The substrate signal path may carry a signal with a frequency that is different than the frequency of a signal that is to be carried by the waveguide. Other embodiments may be described or claimed.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die in a first layer; an interposer in a second layer not coplanar with the first layer, the first layer coupled to the second layer by interconnects having a pitch of less than 10 micrometers between adjacent interconnects; and a first conductive pathway and a second conductive pathway in the interposer coupling the first IC die and a second IC die. The first IC die is configured to transmit at a first supply voltage through the first conductive pathway to a second IC die, the second IC die is configured to transmit to the first IC die through the second conductive pathway at a second supply voltage simultaneously with the first die transmitting at the first supply voltage, and the first supply voltage is different from the second supply voltage.

Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.

Abstract: Embodiments may relate an electronic device that includes a first platform and a second platform coupled with a chassis. The platforms may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first platform and the second platform such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

Abstract: Embodiments disclosed herein include die modules, electronic packages, and electronic systems. In an embodiment, a die module comprises a substrate, where the substrate comprises glass. In an embodiment, a blind cavity is formed into the substrate. In an embodiment, a first die is in the blind cavity, a second die is over the substrate, and a third die is over the substrate and adjacent to the second die.

Abstract: Embodiments disclosed herein include die modules, electronic packages, and systems. In an embodiment, a die module comprises a first substrate and a first die over the first substrate. In an embodiment, the die module further comprises a second die over the first substrate adjacent to the first die. In an embodiment, the die module further comprises a via module through the first substrate. In an embodiment, the via module comprises a second substrate, where the second substrate comprises glass, and a via through the second substrate.

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

Abstract: An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.