Abstract: There may be provided an apparatus, that may include an input/output (IO) circuit; a micro-controller; a memory module that is arranged to store multiple type identification information and multiple type configuration information; wherein the multiple type identification information allows the apparatus to be identified as being of each one of multiple types of peripheral cards; and wherein the multiple type configuration information allows the apparatus to operate each one of the multiple types; wherein the micro-controller is arranged, following a selection of a selected type out of the multiple types: to expose, to a host—that is coupled to the apparatus, a selected portion of the multiple peripheral identification information that indicates that the apparatus has a functionality of a peripheral card of the selected type; and to configure the peripheral card to interact with the host as being a peripheral card of the selected type.

Abstract: A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address in the cache memory, the cache memory divided into a plurality of banks. The method further includes determining a candidate address in each of the cache memory banks using an address determination algorithm, selecting one of the candidate addresses from among the determined candidate addresses using an address selection function different from the address determination algorithm, and returning the selected candidate address in response to the request.

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract: There may be provided an apparatus, that may include an input/output (IO) circuit; a micro-controller; a memory module that is arranged to store multiple type identification information and multiple type configuration information; wherein the multiple type identification information allows the apparatus to be identified as being of each one of multiple types of peripheral cards; and wherein the multiple type configuration information allows the apparatus to operate each one of the multiple types; wherein the micro-controller is arranged, following a selection of a selected type out of the multiple types: to expose, to a host—that is coupled to the apparatus, a selected portion of the multiple peripheral identification information that indicates that the apparatus has a functionality of a peripheral card of the selected type; and to configure the peripheral card to interact with the host as being a peripheral card of the selected type.

Abstract: Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for reducing the likelihood of cache line overlaps in a multi-processor system having a shared memory cache. A transformation function module coupled to the shared memory cache is configured to transform an index associated with a cache operation associated with a processor of the plurality of processors using a transformation function to generate a transformed index. In embodiments, groups of one or more processors have different or unique transformation functions associated with them in order to decrease the tendency or likelihood of their respective cache lines in the shared memory cache to overlap. Other embodiments are also described and claimed.

Abstract: Embodiments of the present disclosure provide a system on a chip (SOC) comprising a processing core, and a cache including a cache instruction port, a cache data port, and a port utilization circuitry configured to selectively fetch instructions through the cache instruction port and selectively pre-fetch instructions through the cache data port. Other embodiments are also described and claimed.

Abstract: Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.

Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a data packet that is transmitted over a network; generating classification information for the data packet; and selecting a memory storage mode for the data packet based on the classification information. Other embodiments are also described and claimed.

Abstract: Some of the embodiments of the present disclosure provide a method comprising receiving a data packet, and storing the received data packet in a memory; generating a descriptor for the data packet, the descriptor including information for fetching at least a portion of the data packet from the memory; and in advance of a processing core requesting the at least a portion of the data packet to execute a processing operation on the at least a portion of the data packet, fetching the at least a portion of the data packet to a cache based at least in part on information in the descriptor. Other embodiments are also described and claimed.