Patents by Inventor Aditya Navale

Aditya Navale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6871119
    Abstract: Machine-readable media, methods, and apparatus are described to throttle interfaces and/or logic based upon a temperature estimate. Some embodiments may provide thermal effects associated with throttled and non-throttled interfaces to a filter. The filter may update a temperature estimate based upon the provided thermal effects and one or more thermal time constants. Control logic may determine whether to throttle one or more interface based upon the temperature estimate of the filter.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: March 22, 2005
    Assignee: Intel Corporation
    Inventors: Eric C. Samson, Aditya Navale, David M. Puffer
  • Patent number: 6862028
    Abstract: A computer graphics system is provided that includes a memory to store image data, a bin pointer list to store information regarding a plurality of image subscenes, and a pointer cache system to maintain data regarding the plurality of image subscenes. The pointer cache system may include a tag array section, a data array section and a decoupling section.
    Type: Grant
    Filed: February 14, 2002
    Date of Patent: March 1, 2005
    Assignee: Intel Corporation
    Inventors: Jonathan B. Sadowski, Aditya Navale
  • Patent number: 6842807
    Abstract: A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved within a certain amount of time. The fetching of this data will cause increased latencies on lower priority clients making requests for data. A method and apparatus for deprioritizing a high priority client is needed to improve the efficiency in handling data traffic requests from both high priority and lower priority clients.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: January 11, 2005
    Assignee: Intel Corporation
    Inventors: Jonathan B. Sadowsky, Aditya Navale
  • Publication number: 20040215371
    Abstract: Machine-readable media, methods, and apparatus are described to throttle interfaces and/or logic based upon a temperature estimate. Some embodiments may provide thermal effects associated with throttled and non-throttled interfaces to a filter. The filter may update a temperature estimate based upon the provided thermal effects and one or more thermal time constants. Control logic may determine whether to throttle one or more interface based upon the temperature estimate of the filter.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Inventors: Eric C. Samson, Aditya Navale, David M. Puffer
  • Publication number: 20040139359
    Abstract: When a processor in a computer system is placed in a low power mode, power consumption of the computer system may be further reduced by reducing power consumption of one or more components of a memory coupled to the processor and by reducing power consumption of one or more components of a controller device coupled to the memory. The processor and the controller device may share the memory.
    Type: Application
    Filed: January 9, 2003
    Publication date: July 15, 2004
    Inventors: Eric C. Samson, Aditya Navale, Richard Jensen, Siripong Sritanyaratana, Win S. Cheng
  • Publication number: 20030210247
    Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Inventors: Ying Cui, Eric C. Samson, Ariel Berkovits, Aditya Navale, David A. Wyatt, Leslie E. Cline, Joseph W. Tsang, Mark A. Blake, David I. Poisner, William A. Stevens, Vijay R. Sar-Dessai
  • Publication number: 20030158982
    Abstract: A method and apparatus of deprioritizing a high priority client. An isochronous data stream request is generally referred to as a “high priority” client. These high priority requests are sensitive to time, such that a certain amount of data must be retrieved within a certain amount of time. The fetching of this data will cause increased latencies on lower priority clients making requests for data. A method and apparatus for deprioritizing a high priority client is needed to improve the efficiency in handling data traffic requests from both high priority and lower priority clients.
    Type: Application
    Filed: February 15, 2002
    Publication date: August 21, 2003
    Inventors: Jonathan B. Sadowsky, Aditya Navale
  • Publication number: 20030151602
    Abstract: A computer graphics system is provided that includes a memory to store image data, a bin pointer list to store information regarding a plurality of image subscenes, and a pointer cache system to maintain data regarding the plurality of image subscenes. The pointer cache system may include a tag array section, a data array section and a decoupling section.
    Type: Application
    Filed: February 14, 2002
    Publication date: August 14, 2003
    Inventors: Jonathan B. Sadowsky, Aditya Navale
  • Publication number: 20030065897
    Abstract: A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams become intermixed, a certain amount of latency results from the resulting page “breaks.” These page breaks occur when consecutive requests are from different data streams, requiring accesses to different memory pages. When several separate streams of data are requested by a client, page coherency between requests diminishes. A reordering device regains lost page coherency, thereby reducing the amount of latency and increasing overall system performance.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Jonathan B. Sadowsky, Aditya Navale