Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract: An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Abstract: Method and circuitry for implementing VCOs with improved frequency band switching use differentially-coupled varactors to implement the different frequency bands. According to a specific embodiment, one side of a varactor couples to the tank circuit and the other side is coupled either to ground or to the positive power supply VDD without introducing any series parasitic resistance.

Abstract: A phase locked loop circuit having a loop filter including a variable resistance for normal loop operation and for fast acquisition has improved stability by defining a loop pole separate from the loop filter. The loop pole remains constant during transition periods of the filter resistance. The loop pole remains constant while loop bandwidth is varied for either phase acquisition or normal operation, and the ratio of bandwidth to pole varies only linearly which makes the phase locked loop more stable during the bandwidth adjustment.

Abstract: A phase locked loop circuit having a loop filter including a variable resistance for normal loop operation and for fast acquisition has improved stability by defining a loop pole separate from the loop filter. The loop pole remains constant during transition periods of the filter resistance. The loop pole remains constant while loop bandwidth is varied for either phase acquisition or normal operation, and the ratio of bandwidth to pole varies only linearly which makes the phase locked loop more stable during the bandwidth adjustment.

Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS) technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.