Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplary embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.

Abstract: Circuits and methods for simplifying clock and data recovery circuits by including a data regeneration circuit as part of a phase detector circuit. Delay elements are added such that the timing of the data recovery is optimized or improved with little or no effect on the clock recovery operation. This allows die area and power supply savings, while retaining the ability to adjust data recovery timing.

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplaxy embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS) technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A timing recovery circuit comprises a data-driven phase detector and a digital loop filter. The data-driven phase detector is operably coupled to determine at least a phase difference between an input signal and a feedback clock signal to produce a difference signal. Determining the phase difference can comprise digitally determining a timing difference between the input signal and the feedback clock signal, digitally determining a transition of the input signal to produce a transition detect signal, and digitally updating the timing difference based on the transition detect signal and the feedback clock signal. The timing difference can be digitally updated by pre-filtering the timing difference BY TAKING EVERY N TRANSITON OR AVERAGE OF EVERY N TRANSITIONS at a digital pre-filter, based on a pre-filter clock signal produced from the transition detect signal and the feedback clock signal, to produce the difference signal.

Abstract: A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal generated by the closed-loop circuitry. Because the voltage generated by the loop filter has a relatively low frequency, the current source/sink is operable at a relatively low frequency. Each current source and current sink may be a current digital-to-analog (DAC). The amount of current sourced into or sunk out of the loop filter by the current DAC is varied by setting the associated bits of a multi-bit signal. If the closed-loop circuitry is differential, a current source is coupled to the loop filter adapted to receive the differentially high signal, and a current source is coupled to the loop filter adapted to receive the differentially low signal.

Abstract: Method and circuitry for implementing VCOs with improved frequency band switching use differentially-coupled varactors to implement the different frequency bands. According to a specific embodiment, one side of a varactor couples to the tank circuit and the other side is coupled either to ground or to the positive power supply VDD without introducing any series parasitic resistance.

Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: A phase locked loop circuit having a loop filter including a variable resistance for normal loop operation and for fast acquisition has improved stability by defining a loop pole separate from the loop filter. The loop pole remains constant during transition periods of the filter resistance. The loop pole remains constant while loop bandwidth is varied for either phase acquisition or normal operation, and the ratio of bandwidth to pole varies only linearly which makes the phase locked loop more stable during the bandwidth adjustment.

Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.