Abstract: Methods and apparatus for pattern matching are disclosed. In at least one embodiment, pattern checking is accomplished by reading a page of memory, and comparing the read page with the pattern to be searched in a logic operation. In at least one other embodiment, a pattern to be searched is stored in registers where each bit of the pattern is stored using two register entries and each bit of the array data is stored using two cells of the array.

Abstract: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.

Abstract: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

Abstract: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.

Abstract: In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit.

Abstract: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.

Abstract: In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip voltage. The trip voltage is set by an architecture of the discharge circuit.

Abstract: Memory devices, memory systems, discharge circuits, and methods for discharging a capacitance are disclosed. In one such memory device, a discharge circuit is coupled to memory support circuitry. When a supply voltage decreases to be less than or equal to a trip voltage, the discharge circuit discharges a voltage from a capacitance of the memory support circuitry.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

Abstract: Memory devices, memory systems, discharge circuits, and methods for discharging a capacitance are disclosed. In one such memory device, a discharge circuit is coupled to memory support circuitry. When a supply voltage decreases to be less than or equal to a trip voltage, the discharge circuit discharges a voltage from a capacitance of the memory support circuitry.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n?1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n?1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n?1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n?1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

Abstract: Embodiments of the present disclosure provide methods, devices, modules, and systems for memory cell sensing using negative voltage. One method includes applying a negative read voltage to a selected access line of an array of memory cells, applying a pass voltage to a number of unselected access lines of the array, and sensing whether a cell coupled to the selected access line is in a conductive state in response to the applied negative read voltage.

Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n?1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n?1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n?1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n?1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.

Abstract: An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is coupled to a negative level shifting circuit to reduce the drain-source stress experienced by transistors in that circuit that are in an off state. The auxiliary voltage generation circuit also generates a logic control signal that indicates to a high voltage discharge path to perform either a slow discharge operation or a fast discharge operation.

Abstract: An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is coupled to a negative level shifting circuit to reduce the drain-source stress experienced by transistors in that circuit that are in an off state. The auxiliary voltage generation circuit also generates a logic control signal that indicates to a high voltage discharge path to perform either a slow discharge operation or a fast discharge operation.

Abstract: An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is coupled to a negative level shifting circuit to reduce the drain-source stress experienced by transistors in that circuit that are in an off state. The auxiliary voltage generation circuit also generates a logic control signal that indicates to a high voltage discharge path to perform either a slow discharge operation or a fast discharge operation.