Abstract: A circuit may include one or more transistors connected directly to an output, and an inductance network. The inductance network may connect to a source node of at least one of the transistors, to compensate capacitance of the output. Thus, the response time of the circuit may decrease, and a non-dominant frequency response pole frequency of the circuit may increase.

Abstract: A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a pulsed, substantially-random signal into a plurality of channels in the ADC. After the substantially-random signal is injected, a gain correlation value is determined for each channel, which value indicates a degree of correlation between the injected substantially-random signal and an output of the respective channel. The gain correlation values are then compared to determine a degree of mismatch between the channels. At least one of the channels is calibrated as a function of the determined degree of mismatch.

Abstract: A method and a corresponding device reduce the convergence time of a correlation algorithm that uses random signals injected into an analog-to-digital converter (ADC) as input to the algorithm. The method and device involve, at a processor of a pipelined ADC, injecting a random signal into each of a plurality of stages in the pipeline and obtaining digital values generated in response to the random signals. Noise components of residue signals in the plurality of stages are calculated as a function of the digital values and values of the random signals. The noise components correspond to the random signals.

Abstract: A method and a corresponding device reduce the convergence time of a correlation algorithm that uses random signals injected into an analog-to-digital converter (ADC) as input to the algorithm. The method and device involve, at a processor of a pipelined ADC, injecting a random signal into each of a plurality of stages in the pipeline and obtaining digital values generated in response to the random signals. Noise components of residue signals in the plurality of stages are calculated as a function of the digital values and values of the random signals. The noise components correspond to the random signals.

Abstract: A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.

Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Abstract: A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into at least one of a flash component and a multiplying digital-to-analog converter (MDAC) in a selected channel in the ADC. A correlation procedure is performed to estimate, based on an overall ADC output, a gain experienced by the injected dither after propagating through the channel. The injection and the correlation procedure are repeated on at least one additional channel to estimate a gain for each at least one additional channel. The estimated gains of the selected channel and the at least one additional channel are then compared to determine a degree of mismatch between the selected channel and each at least one additional channel. At least one channel is calibrated as a function of the determined degree of mismatch.

Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Abstract: An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

Abstract: A method and a corresponding device for reducing inter-channel coupling in a circuit having a plurality of channels includes injecting a randomly determined amount of dither into a first channel of a circuit having a plurality of channels, and after injecting the dither, obtaining an output signal of a second channel in the plurality of channels. A correlation value indicating a degree of correlation between the injected dither and the output signal is determined, and an amount of charge applied to the second channel due to cross-coupling with the first channel is reduced. The amount of the reduction is calculated as a function of the correlation value.

Abstract: A method and device involve a circuit having a switched capacitor network that is switchably connected to an input signal. A randomly determined amount of dither is injected into a circuit having a switched capacitor network that is switchably connected to an input signal. After injecting the dither, at least one correlation value is determined. The correlation value(s) indicates a degree of correlation between the injected dither and an output of the circuit. Distortion caused by an amount of charge kicked back into the circuit when the switched capacitor network is reconnected to the input signal may then be reduced. The reduction is calculated as a function of the correlation value(s).

Abstract: An analog-to-digital converter system that includes a pipeline including N successively-cascaded signal converters, each converting, according to a first clock signal, a respective portion of an input signal of the pipeline into digital codes, a code aligner for receiving and aligning the digital codes from the signal converters in the pipeline into a digital output of the system, an error extractor coupled to an amplifier input node of a selected one signal converter via a first switch for extracting an error signal, and a load system coupled to the amplifier input node of the selected one signal converter via a second switch.

Abstract: A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.

Abstract: A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into at least one of a flash component and a multiplying digital-to-analog converter (MDAC) in a selected channel in the ADC. A correlation procedure is performed to estimate, based on an overall ADC output, a gain experienced by the injected dither after propagating through the channel. The injection and the correlation procedure are repeated on at least one additional channel to estimate a gain for each at least one additional channel. The estimated gains of the selected channel and the at least one additional channel are then compared to determine a degree of mismatch between the selected channel and each at least one additional channel. At least one channel is calibrated as a function of the determined degree of mismatch.

Abstract: A method and a corresponding device for reducing inter-channel coupling in a circuit having a plurality of channels includes injecting a randomly determined amount of dither into a first channel of a circuit having a plurality of channels, and after injecting the dither, obtaining an output signal of a second channel in the plurality of channels. A correlation value indicating a degree of correlation between the injected dither and the output signal is determined, and an amount of charge applied to the second channel due to cross-coupling with the first channel is reduced. The amount of the reduction is calculated as a function of the correlation value.

Abstract: A method and device involve a circuit having a switched capacitor network that is switchably connected to an input signal. A randomly determined amount of dither is injected into a circuit having a switched capacitor network that is switchably connected to an input signal. After injecting the dither, at least one correlation value is determined. The correlation value(s) indicates a degree of correlation between the injected dither and an output of the circuit. Distortion caused by an amount of charge kicked back into the circuit when the switched capacitor network is reconnected to the input signal may then be reduced. The reduction is calculated as a function of the correlation value(s).

Abstract: An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.

Abstract: A process allows for the modification of the least-means-square (LMS) algorithm to remove perturbations associated with measured signals in an analog-to-digital converter (ADC). The process includes measuring the perturbations and determining a coefficient associated with the perturbations. The LMS algorithm is modified in accordance with whether a digital or an analog correction of the inter-stage error of a residue amplifier on the ADC is to be made.

Abstract: An integrated circuit allows for the isolation of the input of an analog-to-digital converter (ADC) from a summing-node (SNS) algorithm. The integrated circuit contains a gating device that is controlled by bits of a flash analog-to-digital converter (ADC) to gate input samples to sub-ranges that are used by the SNS algorithm. A single sub-range is chosen to be used by the SNS algorithm.