Patents by Inventor Ajeet Rohatgi

Ajeet Rohatgi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9153728
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 6, 2015
    Assignee: Suniva, Inc.
    Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
  • Patent number: 8945976
    Abstract: A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides. Metal contacts are applied to the transparent conductive oxide.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: February 3, 2015
    Assignee: Suniva, Inc.
    Inventors: Daniel L. Meier, Ajeet Rohatgi
  • Patent number: 8921968
    Abstract: Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: December 30, 2014
    Assignee: Suniva, Inc.
    Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
  • Publication number: 20120222741
    Abstract: This application discloses silicon solar cells manifesting enhanced light induced degradation characteristics. The application also discloses silicon solar cells with a silicon-based substrate comprising boron, oxygen and carbon, and an antireflective coating (ARC) containing at least one carbon-containing layer adjacent to the substrate. Also disclosed are methods for preparing solar cells.
    Type: Application
    Filed: September 17, 2010
    Publication date: September 6, 2012
    Applicant: L'Air Liquide, Societe Anonyme pour I'Etude et I'Exploitation des Procedes Georges Claude
    Inventors: Michael Davies, Junegie Hong, Genowefa Jakubowska-Okoniewski, Sergiy Navala, Xiaoming Yang, Ajeet Rohatgi, Moon Hee Kang, Abasifreke Udo Ebong, Brian Charles Rounsaville
  • Publication number: 20120171806
    Abstract: A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides Metal contacts are applied to the transparent conductive oxide.
    Type: Application
    Filed: November 30, 2011
    Publication date: July 5, 2012
    Applicant: SUNIVA, INC.
    Inventors: DANIEL L. MEIER, AJEET ROHATGI
  • Publication number: 20120125416
    Abstract: Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 24, 2012
    Applicant: SUNIVA, INC.
    Inventors: AJEET ROHATGI, VIJAY YELUNDUR, PRESTON DAVIS, VINODH CHANDRASEKARAN, BEN DAMIANI
  • Publication number: 20120107998
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Applicant: SUNIVA, INC.
    Inventors: AJEET ROHATGI, VIJAY YELUNDUR, VINODH CHANDRASEKARAN, PRESTON DAVIS, BEN DAMIANI
  • Patent number: 8110431
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: February 7, 2012
    Assignee: Suniva, Inc.
    Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
  • Patent number: 8076175
    Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: December 13, 2011
    Inventors: Daniel L. Meier, Ajeet Rohatgi
  • Patent number: 8071418
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a silicon substrate and introducing dopant to one or more selective regions of the front surface of the substrate by ion implantation. The substrate may be subjected to a single high-temperature anneal cycle. Additional dopant atoms may be introduced for diffusion into the front surface of the substrate during the single anneal cycle. A selective emitter may be formed on the front surface of the substrate such that the one or more selective regions of the selective emitter layer are more heavily doped than the remainder of the selective emitter layer. Associated solar cells are also provided.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: December 6, 2011
    Assignee: Suniva, Inc.
    Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
  • Publication number: 20110139230
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.
    Type: Application
    Filed: June 3, 2010
    Publication date: June 16, 2011
    Inventors: Ajeet Rohatgi, Vijay Yelundur, Vinodh Chandrasekaran, Preston Davis, Ben Damiani
  • Publication number: 20110139231
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include fabricating an n-type silicon substrate and introducing n-type dopant to one or more first and second regions of the substrate so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to form a selective front surface field layer. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. The firing of the back contact may form a p+ emitter layer at the interface of the substrate and back contacts, thus forming a p-n junction at the interface of the emitter layer and the substrate. Associated solar cells are also provided.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 16, 2011
    Inventors: Daniel Meier, Ajeet Rohatgi, Vinodh Chandrasekaran, Vijay Yelundur, Preston Davis, Ben Damiani
  • Publication number: 20110139229
    Abstract: Solar cells and methods for their manufacture are disclosed. An example method may include providing a silicon substrate and introducing dopant to one or more selective regions of the front surface of the substrate by ion implantation. The substrate may be subjected to a single high-temperature anneal cycle. Additional dopant atoms may be introduced for diffusion into the front surface of the substrate during the single anneal cycle. A selective emitter may be formed on the front surface of the substrate such that the one or more selective regions of the selective emitter layer are more heavily doped than the remainder of the selective emitter layer. Associated solar cells are also provided.
    Type: Application
    Filed: June 3, 2010
    Publication date: June 16, 2011
    Inventors: Ajeet Rohatgi, Vijay Yelundur, Preston Davis, Vinodh Chandrasekaran, Ben Damiani
  • Patent number: 7842596
    Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: November 30, 2010
    Assignee: Georgia Tech Research Corporation
    Inventors: Ajeet Rohatgi, Vichai Meemongkolkiat
  • Publication number: 20100233840
    Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed. Briefly described, one exemplary embodiment of the device, among others, includes: a co-fired p-type silicon substrate, wherein the bulk lifetime is about 20 to 125 ?s; an n+ layer formed on the top-side of the p-silicon substrate; a silicon nitride anti-reflective (AR) layer positioned on the top-side of the n+ layer; a plurality of Ag contacts positioned on portions of the silicon nitride AR layer, wherein the Ag contacts are in electronic communication with the n+-type emitter layer; an uniform Al back-surface field (BSF or p+) layer positioned on the back-side of the p-silicon substrate on the opposite side of the p-type silicon substrate as the n+ layer; and an Al contact layer positioned on the back-side of the Al BSF layer. The device has a fill factor (FF) of about 0.75 to 0.85, an open circuit voltage (VOC) of about 600 to 650 mV, and a short circuit current (JSC) of about 28 to 36 mA/cm2.
    Type: Application
    Filed: April 12, 2010
    Publication date: September 16, 2010
    Inventors: Ajeet Rohatgi, Ji-Weon Jeong, Kenta Nakayashiki, Vijay Yelundur, Dong Seop Kim, Mohamed Hilali
  • Patent number: 7790574
    Abstract: Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: September 7, 2010
    Assignee: Georgia Tech Research Corporation
    Inventors: Ajeet Rohatgi, Dong Seop Kim, Kenta Nakayashiki, Brian Rounsaville
  • Publication number: 20100186811
    Abstract: An antireflective coating for silicon-based solar cells comprising amorphous silicon carbonitride, wherein the amount of carbon in the silicon carbonitride is from 5 to 25%, a solar cell comprising the antireflective coating, and a method of preparing the antireflective coating.
    Type: Application
    Filed: August 25, 2009
    Publication date: July 29, 2010
    Applicant: Sixtron Advanced Materials, Inc.
    Inventors: Dong Seop Kim, Moon Hee Kang, Ajeet Rohatgi, Michael Davies, Junegie Hong, Genowefa Jakubowska-Okoniewski, Abasifreke Udo Ebong
  • Patent number: 7741225
    Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: June 22, 2010
    Assignee: Georgia Tech Research Corporation
    Inventors: Ajeet Rohatgi, Vichai Meemongkolkiat
  • Publication number: 20100051096
    Abstract: An antireflective coating for silicon-based solar cells comprising amorphous silicon carbonitride, wherein the amount of carbon in the silicon carbonitride is from 5 to 25%, a solar cell comprising the antireflective coating, and a method of preparing the antireflective coating.
    Type: Application
    Filed: November 28, 2008
    Publication date: March 4, 2010
    Applicant: Sixtron Advanced Materials, Inc.
    Inventors: Dong Seop Kim, Moon Hee Kang, Ajeet Rohatgi, Michael Davies, Junegie Hong, Genowefa Jakubowska-Okoniewski, Abasifreke Ebong
  • Publication number: 20090325327
    Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.
    Type: Application
    Filed: May 6, 2008
    Publication date: December 31, 2009
    Applicant: Georgia Tech Research Corporation
    Inventors: Ajeet Rohatgi, Vichai Meemongkolkiat