Abstract: A thin silicon solar cell having a high quality spin-on dielectric layer is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A first dielectric layer is applied to the rear surface of the silicon wafer using a spin-on process. A high temperature furnace operation provides simultaneous emitter diffusion and front and rear surface passivation. During this high temperature operation, the front emitter is formed, the rear spin-on dielectric layer is cured, and the front dielectric layer is thermally grown. Barrier layers are formed on the dielectric layers. Openings are made in the barrier layers. Contacts are formed in the openings and on the back surface barrier layer.

Abstract: A thin silicon solar cell having a high quality spin-on dielectric layer is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A first dielectric layer is applied to the rear surface of the silicon wafer using a spin-on process. A high temperature furnace operation provides simultaneous emitter diffusion and front and rear surface passivation. During this high temperature operation, the front emitter is formed, the rear spin-on dielectric layer is cured, and the front dielectric layer is thermally grown. Barrier layers are formed on the dielectric layers. Openings are made in the barrier layers. Contacts are formed in the openings and on the back surface barrier layer.

Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.

Abstract: A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.

Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Abstract: A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.

Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.

Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.

Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.

Abstract: Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed.

Abstract: Devices, solar cell structures, and methods of fabrication thereof, are disclosed. Briefly described, one exemplary embodiment of the device, among others, includes: a co-fired p-type silicon substrate, wherein the bulk lifetime is about 20 to 125 ?s; an n+ layer formed on the top-side of the p-silicon substrate; a silicon nitride anti-reflective (AR) layer positioned on the top-side of the n+ layer; a plurality of Ag contacts positioned on portions of the silicon nitride AR layer, wherein the Ag contacts are in electronic communication with the n+-type emitter layer; an uniform Al back-surface field (BSF or p+) layer positioned on the back-side of the p-silicon substrate on the opposite side of the p-type silicon substrate as the n+ layer; and an Al contact layer positioned on the back-side of the Al BSF layer. The device has a fill factor (FF) of about 0.75 to 0.85, an open circuit voltage (VOC) of about 600 to 650 mV, and a short circuit current (JSC) of about 28 to 36 mA/cm2.

Abstract: A preferred embodiment of the electrical power system of the present invention includes a power conditioning unit which is configured to receive the DC electrical output signal to deliver an AC output signal to a grid-connected load. Preferably, the power conditioning unit includes a controller which is configured to monitor the AC output signal so that the power conditioning unit may cease delivering the AC output signal when a characteristic of the AC output signal satisfies an established criterion.

Abstract: Disclosed is an arrangement, dopant source and method used in the fabrication of photocells that minimize handling of cell wafers and involve a single furnace step. First, dopant sources are created by depositing selected dopants onto both surfaces of source wafers. The concentration of dopant that is placed on the surface is relatively low so that the sources are starved sources. These sources are stacked with photocell wafers in alternating orientation in a furnace. Next, the temperature is raised and thermal diffusion takes place whereby the dopant leaves the source wafers and becomes diffused in a cell wafer creating the junctions necessary for photocells to operate. The concentration of dopant diffused into a single side of the cell wafer is proportional to the concentration placed on the respective dopant source facing the side of the cell wafer. Then, in the same thermal cycle, a layer of oxide is created by introducing oxygen into the furnace environment after sufficient diffusion has taken place.

Abstract: Processes which utilize rapid thermal processing (RTP) are provided for inexpensively producing high efficiency silicon solar cells. The RTP processes preserve minority carrier bulk lifetime .tau. and permit selective adjustment of the depth of the diffused regions, including emitter and back surface field (bsf), within the silicon substrate. In a first RTP process, an RTP step is utilized to simultaneously diffuse phosphorus and aluminum into the front and back surfaces, respectively, of a silicon substrate. Moreover, an in situ controlled cooling procedure preserves the carrier bulk lifetime .tau. and permits selective adjustment of the depth of the diffused regions. In a second RTP process, both simultaneous diffusion of the phosphorus and aluminum as well as annealing of the front and back contacts are accomplished during the RTP step.

Abstract: A computer-based deep level transient spectroscopy (DLTS) system (10) efficiently digitizes and analyzes capacitance and conductance transients acquired from a test material (13) by conventional DLTS methods as well as by several transient methods, including a covariance method of linear predictive modeling. A unique pseudo-logarithmic data storage scheme allows each transient to be tested at more than eleven different rates, permitting three to five decades of time constants .tau. to be observed during each thermal scan, thereby allowing high resolution of closely spaced defect energy levels.

Abstract: Processes which utilize rapid thermal processing (RTP) are provided for inexpensively producing high efficiency silicon solar cells. The RTP processes preserve minority carrier bulk lifetime .tau. and permit selective adjustment of the depth of the diffused regions, including emitter and back surface field (bsf), within the silicon substrate. Silicon solar cell efficiencies of 16.9% have been achieved. In a first RTP process, an RTP step is utilized to simultaneously diffuse phosphorus and aluminum into the front and back surfaces, respectively, of a silicon substrate. Moreover, an in situ controlled cooling procedure preserves the carrier bulk lifetime .tau. and permits selective adjustment of the depth of the diffused regions. In a second RTP process, both simultaneous diffusion of the phosphorus and aluminum as well as annealing of the front and back contacts are accomplished during the RTP step.

Abstract: An electrical conductivity tester accurately measures the time-varying electrical conductivity .sigma.(t) and steady-state electrical conductivity .sigma..sub.ss of a test material. In a first embodiment, the transmission phase of a probe circuit is monitored to determine the conductivity of a test material. In the first embodiment, an oscillator circuit generates a reference oscillator signal. A probe circuit receives the reference oscillator signal, magnetically couples to the test material, and modifies the reference oscillator signal via electromagnetic induction to derive a modified transmission phase signal. Finally, a phase detector circuit derives a transmission phase signal by combining the reference oscillator signal and the modified transmission phase signal, the transmission phase signal being directly convertible to the conductivity. In a second embodiment, an amplifier is connected to the probe circuit to form an oscillator circuit.

Abstract: An electrical conductivity tester accurately measures the time-varying electrical conductivity .sigma.(t) and steady-state electrical conductivity .sigma..sub.ss, of a test material. In a first embodiment, the transmission phase of a probe circuit is monitored to determine the conductivity of a test material. In the first embodiment, an oscillator circuit generates a reference oscillator signal. A probe circuit receives the reference oscillator signal, magnetically couples to the test material, and modifies the reference oscillator signal via electromagnetic induction to derive a modified transmission phase signal. Finally, a phase detector circuit derives a transmission phase signal by combining the reference oscillator signal and the modified transmission phase signal, the transmission phase signal being directly convertible to the conductivity. In a second embodiment, an amplifier is connected to the probe circuit to form an oscillator circuit.