Patents by Inventor Ajeet Rohatgi

Ajeet Rohatgi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5462898
    Abstract: A new process has been developed to achieve a very low SiO.sub.x /Si interface state density D.sub.it, low recombination velocity S (<2 cm/s), and high effective carrier lifetime T.sub.eff (>5 ms) for oxides deposited on silicon substrates at low temperature. The technique involves direct plasma-enhanced chemical vapor deposition (PECVD), with appropriate growth conditions, followed by a photo-assisted rapid thermal annealing (RTA) process. Approximately 500-A-thick SiO.sub.x layers are deposited on Si by PECVD at 250.degree. C. with 0.02 W/cm.sup.-2 rf power, then covered with SiN or an evaporated thin aluminum layer, and subjected to a photo-assisted anneal in forming gas ambient at 350.degree. C., resulting in an interface state density D.sub.it in the range of about 1-4.times.10.sup.10 cm.sup.-2 eV.sup.-1, which sets a record for the lowest interface state density D.sub.it for PECVD oxides fabricated to date.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: October 31, 1995
    Assignee: Georgia Tech Research Corporation
    Inventors: Zhizhang Chen, Ajeet Rohatgi
  • Patent number: 5418019
    Abstract: A sequential plasma-enhanced chemical vapor deposition (PECVD) of SiN and SiO.sub.x produces a very effective double-layer antireflection coating. This antireflection coating is compared with the frequently used and highly efficient double-layer MgF.sub.2 /ZnS coating. It is shown that the double-layer SiO.sub.x /SiN coating improves the short-circuited current (J.sub.sc) by 47%, open-circuit voltage (V.sub.oc) by 3.7%, and efficiency (Eff) by 55% for silicon cells with oxide surface passivation. The counterpart MgF.sub.2 /ZnS coating gives smaller improvement in V.sub.oc and Eff. However, if silicon cells do not have the oxide passivation, the PECVD SiO.sub.x /SiN gives much greater improvement in the cell parameters, 57% in J.sub.sc, 8% in V.sub.oc, and 66% in efficiency, compared to the MgF.sub.2 /ZnS coating which improves J.sub.sc by 50%, V.sub.oc by 2%, and cell efficiency by 54%. This significant additional improvement results from the PECVD deposition-induced surface/defect passivation.
    Type: Grant
    Filed: May 25, 1994
    Date of Patent: May 23, 1995
    Assignee: Georgia Tech Research Corporation
    Inventors: Zhizhang Chen, Ajeet Rohatgi
  • Patent number: 4522657
    Abstract: Disclosed is a low temperature technique for annealing implantation damage and activating dopants. Conventional furnace annealing requires temperatures as high as 1000.degree. to 1100.degree. C. to completely anneal the dopant implantation damage; 75 KeV arsenic implantation followed by 550.degree. C. for 75 minutes and 900.degree. C. for 30 minutes in nitrogen for instance is not sufficient to anneal the implantation damage and results in a leakage current of the order of 1 mA per cm.sup.2. If, however, subsequent to the arsenic implantation, 0.4 KeV hydrogen ions are implanted using a Kaufman ion source with an accelerator current of 200 milliamp, then only 500.degree. to 600.degree. C. for one hour anneal in nitrogen is sufficient to eliminate the arsenic implantation damage. This results in a leakage current of the order of 5 to 25 nA per cm.sup.2 and a complete dopant activation is achieved.
    Type: Grant
    Filed: October 20, 1983
    Date of Patent: June 11, 1985
    Assignee: Westinghouse Electric Corp.
    Inventors: Ajeet Rohatgi, Prosenjit Rai-Choudhury, Joseph R. Gigante, Ranbir Singh, Stephen J. Fonash