Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diodes and methods of manufacture. The method includes: forming fin structures with a doped core region, on a substrate material; forming a first color emitting region by cladding the doped core region of a first fin structure of the fin structures, while protecting the doped core regions of a second fin structure and a third fin structure of the fin structures; forming a second color emitting region by cladding the doped core region of the second fin structure, while protecting the doped core regions of the first fin structure and the third fin structure; and forming a third color emitting region by cladding the doped core region of the third fin structure, while protecting the doped core regions of the first fin structure and the second fin structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniform semiconductor nanowire and nanosheet light emitting diodes and methods of manufacture. The structure includes a buffer layer; at least one dielectric layer on the buffer layer, the at least one dielectric layer having a plurality of openings exposing the buffer layer; and a plurality of uniformly sized and shaped nanowires or nanosheets formed in the openings and extending above the at least one dielectric layer.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to finFETs for light emitting diode displays and methods of manufacture. The method includes: forming replacement fin structures with a doped core region, on doped substrate material; forming quantum wells over the replacement fin structures; forming a first color emitting region by doping at least one of the quantum wells over at least a first replacement fin structure of the replacement fin structures, while protecting at least a second replacement fin structure of the replacement fin structures; and forming a second color emitting region by doping another one of the quantum wells over the at least second replacement fin structure of the replacement fin structures, while protecting the first replacement fin structure and other replacement fin structures which are not to be doped.

Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1-xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1-xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1-xN layer in the red LED, the green LED and the blue LED.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to light emitting diode (LED) structures and methods of manufacture. The method includes: forming a buffer layer on a substrate, the buffer layer having at least a lattice mismatch with the substrate; and relaxing the buffer layer by pixelating the buffer layer into discrete islands, prior to formation of a quantum well.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to integrated vertical transistors and light emitting diodes and methods of manufacture. The structure includes a vertically oriented stack of material having a light emitting diode (LED) integrated with a source region and a drain region of a vertically oriented active device.

Abstract: Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to graphene detectors integrated with optical waveguide structures and methods of manufacture. The structure includes a plurality of non-planar fin structures composed of substrate material, and a non-planar sheet of graphene material extending entirely over each of the plurality of non-planar fin structures.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Abstract: A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a plurality of LEDs having LED terminals. An LED bonding surface comprising a dielectric layer with LED bonding surface contact pads is coupled to diode terminals of the LEDs. The backplane (BP) device comprises a BP substrate having top and bottom surfaces. A plurality of system on chip (SoC) chips are bonded to chip pads disposed on a bottom surface of the BP device. The SoC chips are electrically coupled to the CMOS components of the BP device and LEDs of the LED device.

Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1-xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1-xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1-xN layer in the red LED, the green LED and the blue LED.

Abstract: Disclosed is a device which includes first and second major substrate surfaces. The first substrate surface includes an LED with first and second terminals while the second substrate surface includes CMOS circuit components. The CMOS components and LED are coupled by through silicon via (TSV) contacts which extend through the second substrate surface.

Abstract: Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.

Abstract: Devices and methods of forming the devices are disclosed. The device includes a substrate and a color LED pixel disposed on the substrate. The color LED pixel includes a red LED, a green LED and a blue LED. Each of the color LED includes a specific color LED body disposed on the respective color region on the substrate, a specific color multiple quantum well (MQW) on the respective color LED body and a specific color top LED layer disposed over the respective color MQW. The MQWs of the red LED, green LED and blue LED includes at least an indium gallium nitride (InxGa1?xN) layer and a gallium nitride (GaN), where x is the atomic percentage of In in the InxGa1?xN layer, and the MQWs of the red LED, green LED and blue LED have different bandgaps by varying x of the InxGa1?xN layer in the red LED, the green LED and the blue LED.

Abstract: Disclosed is a multi-color semiconductor LED display with integrated with CMOS circuit components, such as thin film transistors (TFTs). LEDs of the display are disposed on a first major surface of a substrate while CMOS circuit components which are configured as circuitry for operating the display are disposed on a second opposing major surface of the substrate. The CMOS components and LEDs are coupled by through silicon via (TSV) contacts through the substrate. Integrating CMOS components with LED on one substrate enhances compactness of the display. Other advantages include low power and low cost with high brightness and resolution desired for portable applications, including virtual reality and augmented reality applications.

Abstract: Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Abstract: A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or SixGe1-x substrate; forming a conformal SiN, SiOxCyNz layer over side and bottom surfaces of the first trenches; filling the first trenches with SiOx; forming a first mask over portions of the Si, Ge, III-V, or SixGe1-x substrate; removing exposed portions of the Si, Ge, III-V, or SixGe1-x substrate, forming second trenches; forming III-V, III-VxMy, or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-VxMy, or Si nanowires and intervening first trenches; removing the SiOx layer, forming third trenches; and removing the second mask.

Abstract: Disclosed are non-planar monolithic hybrid optoelectronic structures. These structures are referred to as non-planar because they contain one or more semiconductor fins. These structures are referred to as monolithic because they contain, within each semiconductor fin, an optical waveguide core positioned laterally between a light sensor and a photodetector. Specifically, each semiconductor fin has end portions and a center portion positioned laterally between the end portions. The center portion is an optical waveguide core and the end portions have trenches that contain the light source and photodetector, respectively. These structures are referred to as hybrid because the optical waveguide core is made of one semiconductor material and the light sensor and photodetector are each made of at least one additional semiconductor material that is different from the semiconductor material of the center portion. Also disclosed herein are methods of forming monolithic non-planar hybrid optoelectronic structures.

Abstract: A method of preventing corner rounding for an alternate channel FINFET formed in trenches and the resulting devices are provided. Embodiments include providing a Si substrate; forming a trench in the Si substrate; forming a Si based layer with a flat upper surface in the trench; and forming a SiGe layer over the Si based layer.