Patents by Inventor Ajit P. Paranjpe
Ajit P. Paranjpe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10985046Abstract: Transfer methods disclosed herein include transferring micro-LEDs from a first carrier to a second carrier. The methods include bonding the micro-LEDs to the first carrier using a first releasable bonding layer that releases when exposed to actinic light. The micro-LEDs are then secured to a second carrier. The first bonding layer is then irradiated through the first releasable bonding layer through the first carrier with the actinic light to release the micro-LEDs from the first carrier. The second carrier can be a display backplane having bonding pads and the micro-LEDs can be secured to the bonding pads.Type: GrantFiled: July 24, 2019Date of Patent: April 20, 2021Assignee: Veeco Instruments Inc.Inventors: Ajit P. Paranjpe, Christopher J. Morath
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Publication number: 20190393069Abstract: Transfer methods disclosed herein include transferring micro-LEDs from a first carrier to a second carrier. The methods include bonding the micro-LEDs to the first carrier using a first releasable bonding layer that releases when exposed to actinic light. The micro-LEDs are then secured to a second carrier. The first bonding layer is then irradiated through the first releasable bonding layer through the first carrier with the actinic light to release the micro-LEDs from the first carrier. The second carrier can be a display backplane having bonding pads and the micro-LEDs can be secured to the bonding pads.Type: ApplicationFiled: July 24, 2019Publication date: December 26, 2019Inventors: Ajit P. Paranjpe, Christopher J. Morath
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Patent number: 9230846Abstract: Wafer carriers and methods for moving wafers in a reactor. The wafer carrier may include a platen with a plurality of compartments and a plurality of wafer platforms. The platen is configured to rotate about a first axis. Each of the wafer platforms is associated with one of the compartments and is configured to rotate about a respective second axis relative to the respective compartment. The platen and the wafer platforms rotate with different angular velocities to create planetary motion therebetween. The method may include rotating a platen about a first axis of rotation. The method further includes rotating each of a plurality of wafer platforms carried on the platen and carrying the wafers about a respective second axis of rotation and with a different angular velocity than the platen to create planetary motion therebetween.Type: GrantFiled: June 6, 2011Date of Patent: January 5, 2016Assignee: Veeco Instruments, Inc.Inventors: Adrian Celaru, Todd A. Luse, Ajit P. Paranjpe, Joseph Scandariato, Qingfu Tang
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Publication number: 20110300297Abstract: Wafer carriers and methods for moving wafers in a reactor. The wafer carrier may include a platen with a plurality of compartments and a plurality of wafer platforms. The platen is configured to rotate about a first axis. Each of the wafer platforms is associated with one of the compartments and is configured to rotate about a respective second axis relative to the respective compartment. The platen and the wafer platforms rotate with different angular velocities to create planetary motion therebetween. The method may include rotating a platen about a first axis of rotation. The method further includes rotating each of a plurality of wafer platforms carried on the platen and carrying the wafers about a respective second axis of rotation and with a different angular velocity than the platen to create planetary motion therebetween.Type: ApplicationFiled: June 6, 2011Publication date: December 8, 2011Applicant: VEECO INSTRUMENTS INC.Inventors: Adrian Celaru, Todd A. Luse, Ajit P. Paranjpe, Joseph Scandariato, Quinfu Tang
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Patent number: 7393561Abstract: A method of increasing ALP briefly, a preferred embodiment of the present invention includes a method of increasing ALP throughput by continuously modulating gas flow in a reactor to achieve layer by layer growth on a wafer. A first reactant is introduced with a percentage of a carrier gas. After a first time interval, the first reactant flow is reduced while the carrier gas flow is increased so as to maintain an approximately constant total gas flow. When the first reactant flow reaches a minimal, predetermined amount, a second reactant flow is initiated and increased while the carrier gas flow is decreased so as to continue a constant total gas flow. The method alternatively includes introducing a substance that enhances reactant adsorption and chemisorption, either as a first applied gas that reacts with the surface or as an added ligand to the reactant. Still further alternatives include a periodic rapid thermo anneal for improving film properties, parallel wafer processing and a reactant reservoir.Type: GrantFiled: January 13, 2003Date of Patent: July 1, 2008Assignee: Applied Materials, Inc.Inventor: Ajit P. Paranjpe
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Patent number: 7037574Abstract: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 ?), pure (impurities<1 at. %), AlOx films with improved breakdown strength (9–10 MV/cm) with a commercially feasible throughput.Type: GrantFiled: May 23, 2001Date of Patent: May 2, 2006Assignee: Veeco Instruments, Inc.Inventors: Ajit P. Paranjpe, Sanjay Gopinath, Thomas R. Omstead, Randhir S. Bubber, Ming Mao
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Patent number: 6905578Abstract: An apparatus and method for depositing plural layers of materials on a substrate within a single vacuum chamber allows high-throughput deposition of structures such as these for GMR and MRAM application. An indexing mechanism aligns a substrate with each of plural targets according to the sequence of the layers in the structure. Each target deposits material using a static physical-vapor deposition technique. A shutter can be interposed between a target and a substrate to block the deposition process for improved deposition control. The shutter can also preclean a target or the substrate and can also be used for mechanical chopping of the deposition process. In alternative embodiments, plural substrates may be aligned sequentially with plural targets to allow simultaneous deposition of plural structures within the single vacuum chamber.Type: GrantFiled: April 27, 1998Date of Patent: June 14, 2005Assignee: CVC Products, Inc.Inventors: Mehrdad M. Moslehi, Cecil J. Davis, Christopher J. Mann, Dwain R. Jakubik, Ajit P. Paranjpe
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Patent number: 6812126Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and time. The barrier can comprises a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: April 21, 2000Date of Patent: November 2, 2004Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Randhir S. Bubber, Lino A. Velo
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Patent number: 6696931Abstract: A retrofittable collision warning apparatus for vehicles comprises a base unit within the vehicle cabin and a plurality of remote units located around the periphery of the vehicle. The remote units generally operate in a low-power sleep mode, and periodically go partially active to listen for wakeup inputs from the base unit, at which time the remote units enter a highest-power active mode to measure the distance between the vehicle and obstacles in the proximity, and use wireless transmission to communicate obstacle position information to the base unit. The base unit accepts operator commands, use wireless communication to transmit control signals to the remote units and receives obstacle position information from the remote units, communicates obstacle position information to the operator through audio and/or visual signals, and controls operation of the collision warning apparatus.Type: GrantFiled: August 24, 2001Date of Patent: February 24, 2004Assignee: Directed Electronics, Inc.Inventor: Ajit P. Paranjpe
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Patent number: 6645847Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: January 30, 2002Date of Patent: November 11, 2003Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Patent number: 6627995Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: GrantFiled: April 1, 2002Date of Patent: September 30, 2003Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., David M. Leet, Sanjay Gopinath
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Patent number: 6596133Abstract: An apparatus and method for the deposition of thin film material layers provides improved use of processing chamber space for enhanced processing capability in the fabrication of microelectronic devices. In one embodiment, a physical-vapor deposition target offset from the processing chamber central axis, such as a target having an annular shape and central opening, deposits a material on a substrate while leaving the central region of the processing chamber available for other deposition techniques, including a centrally located sputtering target, CVD showerhead, or ion source. Alternatively, a collimator divides a processing chamber into sub-chambers and allows energetic species from a PVD target or ion source to pass to a substrate located in a separate sub-chamber for interaction with a CVD precursor without mixing the precursor and the plasma associated with the PVD or ion processes.Type: GrantFiled: June 14, 2001Date of Patent: July 22, 2003Assignee: CVC Products, Inc.Inventors: Mehrdad M. Moslehi, Ajit P. Paranjpe
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Publication number: 20030134038Abstract: A method of increasing ALP briefly, a preferred embodiment of the present invention includes a method of increasing ALP throughput by continuously modulating gas flow in a reactor to achieve layer by layer growth on a wafer. A first reactant is introduced with a percentage of a carrier gas. After a first time interval, the first reactant flow is reduced while the carrier gas flow is increased so as to maintain an approximately constant total gas flow. When the first reactant flow reaches a minimal, predetermined amount, a second reactant flow is initiated and increased while the carrier gas flow is decreased so as to continue a constant total gas flow. The method alternatively includes introducing a substance that enhances reactant adsorption and chemisorption, either as a first applied gas that reacts with the surface or as an added ligand to the reactant. Still further alternatives include a periodic rapid thermo anneal for improving film properties, parallel wafer processing and a reactant reservoir.Type: ApplicationFiled: January 13, 2003Publication date: July 17, 2003Inventor: Ajit P. Paranjpe
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Publication number: 20030003635Abstract: An atomic layer deposition (ALD) process deposits thin films for microelectronic structures, such as advanced gap and tunnel junction applications, by plasma annealing at varying film thicknesses to obtain desired intrinsic film stress and breakdown film strength. The primary advantage of the ALD process is the near 100% step coverage with properties that are uniform along sidewalls. The process provides smooth (Ra˜2 Å), pure (impurities <1 at. %), AlOx films with improved breakdown strength (9-10 MV/cm) with a commercially feasible throughput.Type: ApplicationFiled: May 23, 2001Publication date: January 2, 2003Inventors: Ajit P. Paranjpe, Sanjay Gopinath, Thomas R. Omstead, Randhir S. Bubber, Ming Mao
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Patent number: 6471830Abstract: A system and related method are disclosed for performing an inductively-coupled-plasma ionized physical-vapor deposition (“PVD”) process for depositing material layers onto a substrate. Within a PVD process chamber are contained a target/cathode assembly, a chuck assembly, a process medium, a variable height inductively-coupled (“VHIC”) ionization coil segment and an antenna actuator for controlling the relative vertical position of the variable height inductively-coupled ionization coil segment. The VHIC coil segment can be contained within a dielectric liner and can be covered by a multi-slotted grounded electrostatic shield. The VHIC ionization coil segment can comprise one or more zones comprised of one or more coil loops powered by one or more radio-frequency power supplies. Each zone can be powered through an adjustable passive electrical component for providing multiple inductive zone operations during a deposition process.Type: GrantFiled: October 3, 2000Date of Patent: October 29, 2002Assignee: Veeco/CVC, Inc.Inventors: Mehrdad M. Moslehi, Ajit P. Paranjpe
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Patent number: 6461675Abstract: Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput.Type: GrantFiled: July 10, 1998Date of Patent: October 8, 2002Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Lino A. Velo, Thomas R. Omstead, David R. Campbell, Sr., Zeming Liu, Guihua Shang
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Publication number: 20020137332Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: ApplicationFiled: April 1, 2002Publication date: September 26, 2002Applicant: CVC Products, Inc., a Delware corporationInventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath
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Patent number: 6444103Abstract: Material is deposited from an active shutter onto a substrate located in a processing chamber housing with a shutter target coupled to a shutter target assembly. A first target assembly located in the housing supports a target for physical-vapor deposition of a first material onto the substrate. A shutter is selectively moveable to extend into a closed or activated position and to retract into an open position. The shutter target assembly is coupled to the shutter such that when the shutter is in the closed position, the shutter target assembly is positioned to allow deposition of material from the shutter target onto the substrate. When the shutter is in the open position, the first target is positioned to deposit material onto the substrate. Alternating layers of materials may be deposited by the shutter target and first target by cycling the shutter between an open position and a closed position.Type: GrantFiled: September 15, 2000Date of Patent: September 3, 2002Assignee: CVC Products, Inc.Inventors: Mehrdad M. Moslehi, Yong Jin Lee, Cecil J. Davis, Ajit P. Paranjpe
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Patent number: 6444263Abstract: A method for chemical-vapor deposition of a material film adds precursor decomposition by-product to the precursor flow to suppress premature gas-phase precursor decomposition and improve process repeatability and film quality. In one embodiment, CVD cobalt films are deposited with carbonyl precursors with reduced premature gas-phase reaction and particulate generation by the addition of excess carbon monoxide to the process chamber comprising the precursor flow. The addition of carbon monoxide not only suppresses gas-phase reaction but also improves cobalt film purity. The addition of excess carbon monoxide to CVD cobalt precursor flow provides repeatable deposition of glue and nucleation layers to support CVD copper, and is extendable to the deposition of high purity CVD cobalt for other applications and with other precursors, and also extendable for CVD CoSi2 films and other cobalt-containing applications.Type: GrantFiled: September 15, 2000Date of Patent: September 3, 2002Assignee: CVC Products, Inc.Inventors: Ajit P. Paranjpe, Randhir S. Bubber, Sanjay Gopinath, Thomas R. Omstead, Mehrdad M. Moslehi
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Publication number: 20020102838Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.Type: ApplicationFiled: January 30, 2002Publication date: August 1, 2002Applicant: CVC Products, Inc., a Delaware corporationInventors: Ajit P. Paranjpe, Mehrdad M. Moslehi, Boris Relja, Randhir S. Bubber, Lino A. Velo, Thomas R. Omstead, David R. Campbell, David M. Leet, Sanjay Gopinath