Abstract: The present invention provides compounds and compositions for inhibiting Vif and methods for treating viral infection, e.g., HIV infection.

Abstract: A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.

Abstract: In accordance with one embodiment of the present invention, there are provided mechanisms and methods for providing an application programming interface (API) for managing applications deployed on one or more servers. These mechanisms and methods can enable a software developer to create a single program that can discover and browse resources, such as JDBC connection pools, deployed applications and other resources, on any J2EE Application server, for example. In an embodiment, the APIs are part of the J2EE Management Specification, which specifies interface mechanisms for J2EE Application servers to describe their resources using a standard data model. Embodiments employing APIs conforming to the J2EE Management Specification can enable third party software, for example, to be used to monitor the applications.

Abstract: In one embodiment, services are not loaded if they are not needed by the user and if no services needed by the user are dependent upon them. In one embodiment, server services are represented as nodes in a graph data structure. Connections between the nodes indicate dependencies between the server services. The graph is sorted to create an ordered list of services which can be used to startup the services. In another embodiment a server services manager reads license files and user inputs and marks the ordered list of services to indicate which services are to startup.

Abstract: In one embodiment a light weight server installer is provided which enables a user to install a Java Platform Enterprise Edition compatible application server with no additional functionality. The user can then select the functionality he or she requires and the light weight server installer installs only the components necessary to implement the selected functionality. In another embodiment the user uses a graphical user interface to make his or her selections. In another embodiment the light weight server installer is an internet installer, enabling the user to download over the internet only the components necessary to implement the selected functionality.

Abstract: According to one exemplary embodiment, a frequency synthesizer module includes a loop filter, where the loop filter includes a capacitor having a first terminal and a second terminal. The frequency synthesizer module further includes a loop filter calibration module coupled to the capacitor in the loop filter. The loop filter calibration module causes an initial capacitance between the first terminal and the second terminal of the capacitor to increase to a target capacitance when the loop filter is in a calibration mode. The target capacitance can causes in increase in control of a bandwidth of the loop filter and a reduction in percent error of a unity gain bandwidth of the loop filter. The loop filter further includes a switched capacitor array configured to cause the initial capacitance to increase to the target capacitance in response to a digital feedback signal provided by the loop filter calibration module.

Abstract: According to one exemplary embodiment, a frequency synthesizer module includes a loop filter, where the loop filter includes a capacitor having a first terminal and a second terminal. The frequency synthesizer module further includes a loop filter calibration module coupled to the capacitor in the loop filter. The loop filter calibration module causes an initial capacitance between the first terminal and the second terminal of the capacitor to increase to a target capacitance when the loop filter is in a calibration mode. The target capacitance can causes in increase in control of a bandwidth of the loop filter and a reduction in percent error of a unity gain bandwidth of the loop filter. The loop filter further includes a switched capacitor array configured to cause the initial capacitance to increase to the target capacitance in response to a digital feedback signal provided by the loop filter calibration module.

Abstract: A system for direct modulation is disclosed. Embodiments of the direct modulator for shift-keying modulation include impressing baseband data on a radio frequency (RF) signal at an oscillator by controlling a digital divider using a sigma-delta modulator.

Abstract: A system for direct modulation is disclosed. Embodiments of the direct modulator for shift-keying modulation include impressing baseband data on a radio frequency (RF) signal at an oscillator by controlling a digital divider using a sigma-delta modulator.

Abstract: A synchronous prescaler is provided that has an input line for receiving an input signal, which is synchronized to a low order dual modulus prescaler. The dual modulus prescaler generally divides responsive to a mode command line, but may have a dead-zone period where it may fail to respond to a generated mode command. The dual modulus prescaler also has an output line that is synchronized to an extender section. The extender section is used to further divide the input signal, and is synchronized to an adjustable counter section. A sync controller circuit receives an output from the counter section, as well as a timing signal from the extender, and generates the mode signal on the mode command line. In this arrangement, the sync controller generates the mode signal at a time when the low order dual modulus is in a condition to change divide modes, thereby avoiding providing the signal during the dead-zone period.

Abstract: A highly agile low phase noise frequency synthesizer is provided for rapid generation of frequency specific signals. The frequency synthesizer is capable of rapidly generating signals at different output frequencies while maintaining low cross-coupling. Two or more signal generators utilize a reference frequency to generate two or more signals. These signals are limit processed to reduce cross-coupling prior to being presented to a switch. Responsive to a control signal, the switch outputs one of the signals to a frequency modification device, such as a frequency divider or multiplier. Responsive to a control signal, the frequency modification device scales the frequency of the switch output to convert the frequency of the switch output signal to a desired output frequency. By maintaining sufficient frequency separation between the switch input signals cross-coupling and phase noise is minimized and implementation on an integrated circuit may be achieved.

Abstract: A low power charge pump is provided that has complementary transistors capable of isolating switching noise from the input switching transistors. The charge pump uses charged currents that are matched in both magnitude and time to reduce switching noise in the output of the charge pump. The charge pump is also designed for use in a phase lock loop.

Abstract: A low power charge pump is provided that has complementary transistors capable of isolating switching noise from the input switching transistors. The charge pump uses charged currents that are matched in both magnitude and time to reduce switching noise in the output of the charge pump. The charge pump is also designed for use in a phase lock loop.

Abstract: A low power voltage-to-current converter is provided for use in a phase lock loop circuit. The low power voltage-to-current converter includes an input stage, and output stage, and a non-differential output terminal. The input stage includes a pair of differential signal input terminals to receive a differential input signal pair, a first and second switching transistor pair coupled to the differential input signal pair, and a first and second complementary transistor pair coupled to the first and second switching transistor pair. The output stage is coupled to the first complementary transistor. The non-differential output terminal is coupled to the output stage, and is operable to transmit an output current signal, wherein the output current signal is a function of the differential input signals. The voltage-to-current converter is also designed for use in a phase lock loop.

Abstract: A microwave monolithic integrated circuit assembly includes a microwave monolithic integrated circuit having an MMIC circuit plane and having a first region of relatively high heat production and a second region of relatively low heat production. A heat-dissipating assembly is in thermal contact with the microwave monolithic integrated circuit. The heat-dissipating assembly has at least two pieces of pyrolytic graphite embedded within a casing. The pieces of pyrolytic graphite include a first piece of pyrolytic graphite underlying the first region and having a high-thermal-conductivity x-direction of the first piece lying within about 20 degrees of a perpendicular to the MMIC circuit plane, and a second piece of pyrolytic graphite underlying the second region and having a high-thermal-conductivity x-direction of the second piece lying within about 20 degrees of the MMIC circuit plane. The heat-dissipating assembly is preferably fabricated by hot isostatic pressing.

Abstract: A microwave monolithic integrated circuit assembly includes a microwave monolithic integrated circuit having an MMIC circuit plane and having a first region of relatively high heat production and a second region of relatively low heat production. A heat-dissipating assembly is in thermal contact with the microwave monolithic integrated circuit. The heat-dissipating assembly has at least two pieces of pyrolytic graphite embedded within a casing. The pieces of pyrolytic graphite include a first piece of pyrolytic graphite underlying the first region and having a high-thermal-conductivity x-direction of the first piece lying within about 20 degrees of a perpendicular to the MMIC circuit plane, and a second piece of pyrolytic graphite underlying the second region and having a high-thermal-conductivity x-direction of the second piece lying within about 20 degrees of the MMIC circuit plane. The heat-dissipating assembly is preferably fabricated by hot isostatic pressing.

Abstract: A low power charge pump is provided that has complementary transistors capable of isolating switching noise from the input switching transistors. The charge pump uses charged currents that are matched in both magnitude and time to reduce switching noise in the output of the charge pump. The charge pump is also designed for use in a phase lock loop.

Abstract: A packaged electronic structure includes an electronic device, and a package to which the electronic device is affixed. At least a portion of the package is made of a composite material of aluminum nitride dispersed in aluminum. The composite material is preferably prepared by mixing powders of the aluminum nitride and aluminum, and thereafter pressing and sintering the mixture.

Abstract: An oscillator has a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, a swing-fixing circuit that fixes the swing of the control signal, and a switching block that generates an output signal having a frequency derived from the swing and the slope of the control signal. The slope-fixing circuit comprises a fixed timing capacitor C1 in parallel with a plurality of switchable timing capacitors C2 . . . CN to provide an effective capacitance C. The slope of the control signal is determined by the ratio of a control current I to the effective capacitance C. The swing-fixing circuit comprises a replica cell that accepts a programmable reference voltage VREF and provides a fixed voltage swing VSW=VDD−VREF across a pair of load transistors. The switching block comprises a pair of switching transistors that alternate between “on” and “off” states depending on the value of the control signal to produce an oscillating output signal.

Abstract: The present invention relates to a circuit for protecting inputs and outputs on semiconductor devices. The protective circuit is particularly useful on high-speed inputs or outputs (such as in radio frequency applications where signal frequency is on the order of 100 MHz or greater and where it is necessary to minimize capacitive loading. Briefly, the present invention utilizes two FETs to shunt harmful electrostatic charges to a low impedance power bus and protect input and output circuit elements from damage or degradation. When a high voltage transient surge is detected, the drain-gate capacitance of one of the FETs couples the voltage to the gate electrode and biases one of the two transistors in the low impedance state so that the surge is absorbed without damage to the input or output circuit. Significantly, the capacitive loading of the protection circuit of the present invention is typically a fraction of a picoFarad and more particularly on the order of several hundred femtofarads.