Abstract: A low power charge pump is provided that has complementary transistors capable of isolating switching noise from the input switching transistors. The charge pump uses charged currents that are matched in both magnitude and time to reduce switching noise in the output of the charge pump. The charge pump is also designed for use in a phase lock loop.

Abstract: A packaged electronic structure includes an electronic device, and a package to which the electronic device is affixed. At least a portion of the package is made of a composite material of aluminum nitride dispersed in aluminum. The composite material is preferably prepared by mixing powders of the aluminum nitride and aluminum, and thereafter pressing and sintering the mixture.

Abstract: An oscillator has a slope-fixing circuit that generates a control signal and fixes the slope of the control signal, a swing-fixing circuit that fixes the swing of the control signal, and a switching block that generates an output signal having a frequency derived from the swing and the slope of the control signal. The slope-fixing circuit comprises a fixed timing capacitor C1 in parallel with a plurality of switchable timing capacitors C2 . . . CN to provide an effective capacitance C. The slope of the control signal is determined by the ratio of a control current I to the effective capacitance C. The swing-fixing circuit comprises a replica cell that accepts a programmable reference voltage VREF and provides a fixed voltage swing VSW=VDD−VREF across a pair of load transistors. The switching block comprises a pair of switching transistors that alternate between “on” and “off” states depending on the value of the control signal to produce an oscillating output signal.

Abstract: The present invention relates to a circuit for protecting inputs and outputs on semiconductor devices. The protective circuit is particularly useful on high-speed inputs or outputs (such as in radio frequency applications where signal frequency is on the order of 100 MHz or greater and where it is necessary to minimize capacitive loading. Briefly, the present invention utilizes two FETs to shunt harmful electrostatic charges to a low impedance power bus and protect input and output circuit elements from damage or degradation. When a high voltage transient surge is detected, the drain-gate capacitance of one of the FETs couples the voltage to the gate electrode and biases one of the two transistors in the low impedance state so that the surge is absorbed without damage to the input or output circuit. Significantly, the capacitive loading of the protection circuit of the present invention is typically a fraction of a picoFarad and more particularly on the order of several hundred femtofarads.

Abstract: A differential LC-based voltage-controlled oscillator (LC-VCO), charge pump and loop filter architecture for providing improved noise immunity in integrated phase-locked loops (PLLs). A pair of voltage control signals are provided from a differential charge pump and loop filter architecture to respective voltage control inputs in the LC-VCO to differentially control the LC-VCO. The voltage control inputs are connected to respective terminals on opposite ends of a varactor tuning circuit. The differential voltage applied across the varactor tuning circuit determines the LC characteristics of the varactor tuning circuit which, in turn, determines the operating frequency of the VCO. One of the voltage control inputs is passed through an operational amplifier buffering stage before being transmitted to its respective terminal in the varactor tuning circuit. The LC-VCO utilizes a PMOS transistor core to provide good substrate isolation and low flicker (1/f) noise.

Abstract: RF voltage amplifier circuits which have high voltage amplifier gain and input signal frequency range, and a method for boosting the voltage amplifier gain and input signal frequency range in such circuits is provided. A method includes the steps of providing a voltage amplifier having a transistor with the grounded source and the drain connected to a power supply via a resistive load, and providing an integrated inductor for biasing the transistor, having an inductor connecting an input signal terminal to the gate of the transistor and a capacitor connecting the gate and the source of the transistor. The next step includes selecting a resonant frequency of the integrated inductor at a frequency where the voltage amplifier gain is starting to roll-off, for boosting the voltage amplifier gain and the input signal frequency range. The integrated inductor preferably operates at a resonant frequency approximately matching the roll-off frequency of the voltage amplifier.

Abstract: In a phase lock loop, a charge pump includes a current mirror circuit. The current mirror circuit contains a bias current source and a current mirror source which mirrors the current of the bias current source. The current mirror source is turned on and off in accordance with an output signal from a phase detector to produce correction signals for a VCO. To conserve power, circuits are provided for turning the bias current source on just before it is needed by the current mirror source and for turning the bias current source off just after the current mirror source turns off.

Abstract: A phase-locked loop includes a phase/frequency detector, a charge pump, a loop filter, an oscillator and a feedback circuit coupled between the oscillator and the phase/frequency detector. The loop filter includes a first temperature-variable well resistor and has a gain directly related to resistance of the first resistor. An oscillator coupled to the loop filter includes a voltage-to-current converter that generates a reference current based on the loop filter voltage, and a current-controlled oscillator that generates the output clock based on the value of the reference current. The voltage-to-current converter includes a first transistor that receives the loop filter voltage at a gate and a second temperature-variable well resistor coupled to the source of the first transistor. The oscillator gain is indirectly related to the resistance of the second resistor. The second well resistor and first well resistor have substantially equal resistances and substantially equal temperature coefficients.

Abstract: A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N−1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

Abstract: A D flip-flop circuit operating in master-slave configuration which has low power consumption and is capable of high-speed operation, and a method for lowering power consumption in such a circuit is provided. The circuit embodiment includes two latches, each with a switching and memory section, and two interlaced current sources. In response to the active high clock signal the master latch memory section uses the current from the first current source while the slave latch switching section uses the current from the second current source, and vice versa. The switching section of each latch is biased with a higher current than the memory section, to provide the circuit with low power consumption. The output current provided to the switching section is preferably substantially twice the magnitude of the current provided to the memory section. The ratio of the currents of the current sources for the switching and memory section is preferably in the range of about 30% to 70%, depending on the clock frequency.

Abstract: A phase locked loop (PLL) circuit with time-delayed phase/frequency detector (PFD) input signals and a method for generating high PFD gain in such a circuit is provided. One circuit embodiment includes a first divider, a phase/frequency detector having a plurality of input pairs, a plurality of input signal reference delay elements connected in a series between the first divider and the PFD, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a second divider, and a plurality of feedback signal delay elements connected in a series. The corresponding method embodiment includes steps for receiving digital input signals with reference frequency and period T in the first divider, dividing the reference frequency by a value R, providing a plurality of time-delayed PFD reference input signals in each period T, dividing the VCO frequency by a value M in the second divider, and providing a plurality of time-delayed PFD feedback input signals in each period T.

Abstract: An electronic structure includes an electronic device, and a heat sink assembly in thermal contact with the electronic device. The heat sink assembly is formed of a piece of pyrolytic graphite embedded within a metallic casing and intimately contacting an interior wall of the metallic casing. The heat sink assembly is substantially fully dense. The heat sink assembly is fabricated by assembling the piece of pyrolytic graphite within the disassembled elements of the metallic casing, and then simultaneously heating and pressing the initial assembly until it is substantially fully dense.

Abstract: A phased array (20) and method for constructing the same are disclosed. The phased array (20) includes a superstructure (22) with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) and cooperates with the cavities (40) to form cavity style filters therebetween and to form a box-beam type superstructure. Ideally, the superstructure (22) is self supporting. Electronic modules (32) and amplifiers (33) are mounted to the superstructure (22). The method includes machining a block of material to form a webbed superstructure with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) over the cavities (40) to form cavity style filters. Amplifiers (32) and antenna elements (30) are then affixed to the superstructure (22) and cover plate (28). Ideally, the cover plate (28) is affixed to the superstructure (22) using an electrically conductive adhesive.

Abstract: A multiple input, low voltage, OR/NOR gate architecture based on a single-ended OR/NOR gate circuit, wherein a plurality of input transistors are connected in parallel. A reference transistor connects to the input transistors. A feedback means connects the NOR output signal to the base or gate of the reference transistor. The feedback means provides an effectively differential input for the multiple input circuit, without increasing circuit complexity, thereby providing enhanced noise margin characteristics.

Abstract: A ceramic-polymer composite material such as part of a microelectronics package is formed of a ceramic mixture of aluminum nitride and boron nitride, and a low-loss polymeric material. The amount of aluminum nitride is preferably from about 50 to about 90 weight percent of the ceramic mixture, but the relative amounts of the two ceramics may be adjusted to achieve thermal expansion and thermal conductivity properties required for a particular application. A mixture of the ceramics and uncured thermosetting polymeric resin is formed, pressed into the shape of the microelectronics base and/or lid, and heated (either concurrently or subsequently) to compress the mixture and cure the polymer.

Abstract: An electronic structure is formed of alternating layers of a metal and a cured ceramic-polymer mixture. The ceramic-polymer mixture is prepared by mixing small ceramic particles into a flowable, curable polymer. The mixture is spread over a first metallic layer and, optionally, B-stage cured. Additional metallic layers and ceramic-polymer layers are added in alternating fashion. Metallic interconnects may be provided through overlying ceramic-polymer layers to a particular metallic layer. The resulting structure is heated to a moderate temperature to cure the polymer.

Abstract: A phased array (20) and method for constructing the same are disclosed. The phased array (20) includes a superstructure (22) with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) and cooperates with the cavities (40) to form cavity style filters therebetween and to form a box-beam type superstructure. Ideally, the superstructure (22) is self supporting. Electronic modules (32) and amplifiers (33) are mounted to the superstructure (22). The method includes machining a block of material to form a webbed superstructure with cavities (40) therein. A cover plate (28) is mounted to the superstructure (22) over the cavities (40) to form cavity style filters. Amplifiers (32) and antenna elements (30) are then affixed to the superstructure (22) and cover plate (28). Ideally, the cover plate (28) is affixed to the superstructure (22) using an electrically conductive adhesive.

Abstract: A packaged electronic structure includes an electronic device, and a package to which the electronic device is affixed. At least a portion of the package is made of a composite material of aluminum nitride dispersed in aluminum. The composite material is preferably prepared by mixing powders of the aluminum nitride and aluminum, and thereafter pressing and sintering the mixture.