Patents by Inventor Akifumi Gawase

Akifumi Gawase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8871644
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device comprises forming a to-be-processed film includes a convex potion and concave potion on its surface on a semiconductor substrate via layers having a relative dielectric constant smaller than that of SiO2, planarizing the surface of the to-be-processed film, and etching the planarized surface of the to-be-processed film.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Akifumi Gawase, Gaku Minamihaba
  • Publication number: 20140287586
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device comprises forming a to-be-processed film includes a convex potion and concave potion on its surface on a semiconductor substrate via layers having a relative dielectric constant smaller than that of SiO2, planarizing the surface of the to-be-processed film, and etching the planarized surface of the to-be-processed film.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukiteru MATSUI, Akifumi GAWASE, Gaku MINAMIHARA
  • Publication number: 20140220778
    Abstract: According to one embodiment, a planarization method and a planarization apparatus are provided. In the planarization method, a work surface of a work piece is planarized by bringing the work surface of the work piece containing a silicon oxide film and a surface of a solid plate onto which hydrogen ions are adsorbed, into contact or extremely close proximity with one another in a state in which a process liquid containing fluorine ions is supplied to the surface of the solid plate.
    Type: Application
    Filed: September 9, 2013
    Publication date: August 7, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akifumi GAWASE, Yukiteru Matsui, Gaku Minamihaba, Hajime Eda
  • Publication number: 20140187042
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Application
    Filed: March 6, 2014
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kodera, Hiroshi Tomita, Gaku Minamihaba, Akifumi Gawase
  • Patent number: 8703004
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kodera, Hiroshi Tomita, Gaku Minamihaba, Akifumi Gawase
  • Publication number: 20140073136
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises forming an interlayer dielectric film on a semiconductor substrate, forming a film on the interlayer dielectric film to cover a recess and projection formed on a surface of the interlayer dielectric film, polishing the film by CMP to expose the interlayer dielectric film, and etching the film and the interlayer dielectric film such that etching rates of the film and the interlayer dielectric film are equal.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 13, 2014
    Inventors: Gaku MINAMIHABA, Akifumi Gawase, Yukiteru Matsui
  • Publication number: 20140004628
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a wiring groove on an insulating film; forming a barrier metal layer and a metal layer; polishing the metal layer by applying a first load on the metal layer; and subsequently polishing the metal layer while applying a second load larger than the first load on the metal layer and spraying a gas onto a polishing pad. The polishing pad is in contact with the metal layer. The barrier metal layer covers an upper surface of the insulating film and an inner surface of the wiring groove, and the metal layer fills an inside of the wiring groove and covers the barrier metal layer.
    Type: Application
    Filed: February 27, 2013
    Publication date: January 2, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hajime EDA, Gaku Minamihaba, Yukiteru Matsui, Akifumi Gawase
  • Publication number: 20130331004
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises forming a film to be polished on a semiconductor substrate, and performing a CMP method on the film to be polished. The CMP method includes polishing the film to be polished by bringing a surface of the film to be polished into contact with a surface of a polishing pad having a negative Rsk value.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 12, 2013
    Inventors: Gaku MINAMIHABA, Akifumi Gawase, Hajime Eda, Yukiteru Matsui, Satoshi Kamo, Naoki Nishiguchi, Ayako Maekawa
  • Publication number: 20130331005
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises conditioning a polishing pad by pressing a dresser against a surface of the polishing pad while keeping a surface temperature of the polishing pad at 40° C. or higher, and chemically mechanically polishing a polishing target film formed on a semiconductor substrate by pressing a surface of the polishing target film against the surface of the polishing pad having a negative Rsk value.
    Type: Application
    Filed: March 14, 2013
    Publication date: December 12, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akifumi GAWASE, Gaku MINAMIHABA, Hajime EDA, Yukiteru MATSUI
  • Publication number: 20130157464
    Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.
    Type: Application
    Filed: September 5, 2012
    Publication date: June 20, 2013
    Inventors: Akifumi GAWASE, Yukiteru Matsui
  • Publication number: 20130119013
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Application
    Filed: March 16, 2012
    Publication date: May 16, 2013
    Inventors: Yukiteru MATSUI, Masako KODERA, Hiroshi TOMITA, Gaku MINAMIHABA, Akifumi GAWASE
  • Publication number: 20130095661
    Abstract: According to one embodiment, a CMP method includes starting a polishing of a silicon oxide film by using a slurry including a silicon oxide abrasive and a polishing stopper film including a silicon nitride film, and stopping the polishing when the polishing stopper is exposed. The slurry includes a first water-soluble polymer with a weight-average molecular weight of 50000 or more and 5000000 or less, and a second water-soluble polymer with a weight-average molecular weight of 1000 or more and 10000 or less.
    Type: Application
    Filed: March 23, 2012
    Publication date: April 18, 2013
    Inventors: Akifumi GAWASE, Yukiteru Matsui, Gaku Minamihaba, Hajime Eda
  • Publication number: 20130078784
    Abstract: According to one embodiment, the CMP slurry includes abrasive particles made of colloidal silica in an amount of 0.5 to 3% by mass of a total mass of the CMP slurry, and a polycarboxylic acid having a weight average molecular weight of from 500 to 10,000, in an amount of 0.1 to 1% by mass of the total mass of the CMP slurry. 50 to 90% by mass of the abrasive particles each has a primary particle diameter of 3 to 10 nm. The CMP slurry has a pH within a range of 2.5 to 4.5.
    Type: Application
    Filed: March 21, 2012
    Publication date: March 28, 2013
    Inventors: Gaku MINAMIHABA, Akifumi Gawase, Yukiteru Matsui, Hajime Eda
  • Publication number: 20130040456
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a groove is formed in a insulating film on a semiconductor substrate. An underlayer film is formed on the insulating film. A metal film is formed on the underlayer film. First polishing, in which the metal film is removed, is performed by supplying a first CMP slurry containing metal ions. The surfaces of the polishing pad and the semiconductor substrate are cleaned by supplying organic acid and pure water. Second polishing, in which the underlayer film is removed from the portion other than the groove, is performed by supplying a second CMP slurry different from the first CMP slurry.
    Type: Application
    Filed: March 23, 2012
    Publication date: February 14, 2013
    Inventors: Hajime EDA, Yukiteru Matsui, Gaku Minamihaba, Akifumi Gawase
  • Publication number: 20120220195
    Abstract: According to one embodiment, a CMP apparatus includes a supplying portion supplying a slurry to a surface portion of a polishing pad including water-soluble particles, a holding portion contacting an object to be polished with the surface portion of the polishing pad in a condition of holding the object, a temperature setting portion on the surface portion of the polishing pad, the temperature setting portion setting a temperature of the surface of the polishing pad. A control portion executes a first polishing step and a second polishing step after the first polishing step, the object is polished in a condition of setting the temperature of the surface of the polishing pad within a first temperature range in the first polishing step, and the object is polished in a condition of setting the temperature of the surface of the polishing pad within a second temperature range in the second polishing step.
    Type: Application
    Filed: September 15, 2011
    Publication date: August 30, 2012
    Inventors: Akifumi GAWASE, Yukiteru Matsui
  • Patent number: 7781301
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming an interlayer sacrificial film and an insulating film located thereon above a semiconductor substrate having a semiconductor element, the interlayer sacrificial film having a wiring provided therein; etching the insulating film, or, etching the insulating film and the interlayer sacrificial film to form a trench reaching the interlayer sacrificial film; forming a gas permeable film in the trench; gasifying and removing the interlayer sacrificial film through the trench and the gas permeable film; and forming a sealing film on the gas permeable film for sealing the vicinity of an opening of the trench after removing the interlayer sacrificial film.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: August 24, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Watanabe, Akifumi Gawase, Kenichi Otsuka
  • Publication number: 20100055893
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming an interlayer sacrificial film and an insulating film located thereon above a semiconductor substrate having a semiconductor element, the interlayer sacrificial film having a wiring provided therein; etching the insulating film, or, etching the insulating film and the interlayer sacrificial film to form a trench reaching the interlayer sacrificial film; forming a gas permeable film in the trench; gasifying and removing the interlayer sacrificial film through the trench and the gas permeable film; and forming a sealing film on the gas permeable film for sealing the vicinity of an opening of the trench after removing the interlayer sacrificial film.
    Type: Application
    Filed: August 6, 2009
    Publication date: March 4, 2010
    Inventors: Kei WATANABE, Akifumi Gawase, Kenichi Otsuka