Abstract: A database search system receives a command and searches for data, which meets a search condition specified on the basis of the received command, in a whole database which is a database as an entity. The database search system generates a virtual database which is a list of address pointers to the found data and stores the generated virtual database.

Abstract: The present invention improves an access performance in an SSD device in which a nonvolatile semiconductor, such as a NAND flash memory, is mounted, or in a storage subsystem having the SSD device built therein, and achieves longer operating life. For this purpose, a plurality of units (logical-physical sizes) for associating a logical address with a physical address is provided in the SSD device or the storage subsystem, and an appropriate logical-physical size is selected in accordance with an I/O size or I/O pattern accessed from a superior device.

Abstract: A computer system according to one preferred embodiment of the present invention has a server and a storage subsystem, wherein the server is configured to enable data write to a cache area of the storage subsystem. Further, the server manages the usages of the cache area. When storing data from the server to the cache area, the server determines whether a data-writable area exists in the cache area or not. If there is a writable area, data is stored in the writable area.

Abstract: A storage apparatus has a plurality of hardware engines which send and receive information to and from a controller, which, on the condition of acquiring a request command from a host, determines identifying information of the request command, executes data I/O processing to the storage device according to the request command when first identifying information has been added to the request command and when second identifying information has been added to the acquired request command, transfers the request command to the hardware engine, acquires the data requested by the hardware engine from the storage device and transfers the acquired data to the hardware engine. The hardware engine acquires and analyzes an add-on command from the host and according to the request command, requests the controller to transfer the data based on the analysis result, and thereafter executes processing to the data transferred by the controller according to the add-on command.

Abstract: A management controller controls a data buffer and a flash controller, which controls I/O of data to and from flash memories, based on a search request. A data decompression engine includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer. A data search engine includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions among the respective data that were decompressed by the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data requested in the search request, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine when the compressed data is stored in the data buffer.

Abstract: A data memory device has a command transfer direct memory access (DMA) engine configured to obtain a command that is generated by an external apparatus to give a data transfer instruction from a memory of the external apparatus; obtain specifics of the instruction; store the command in a command buffer; obtain a command number that identifies the command being processed; and activate a transfer list generating DMA engine by transmitting the command number depending on the specifics of the instruction of the command. The transfer list generating DMA engine is configured to: identify, based on the command stored in the command buffer, an address in the memory to be transferred between the external apparatus and the data memory device; and activate the data transfer DMA engine by transmitting the address to the data transfer DMA engine which then transfers the data to/from the memory based on the received address.

Abstract: A turn lamp to be mounted on a door mirror of a vehicle, the turn lamp includes a housing; a light source; and a substrate having a feeder circuit for the light source, wherein: the substrate is placed in the housing such that a plane direction of the substrate faces a horizontal direction when the door mirror is mounted to a vehicle body, and the light source is placed on the substrate such that an irradiation direction of the light source is parallel to the plane direction of the substrate.

Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.

Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

Abstract: A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple blocks, which are data erase units, and each block comprises multiple pages, which are data write and read units. The cache controller receives data and attribute information of the data, and, based on the received attribute information and attribute information of the data stored in the multiple blocks, selects a storage-destination block for storing the received data, and writes the received data to a page inside the selected storage-destination block.

Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

Abstract: The degree of deterioration of each physical storage area in a non-volatile memory is evaluated without interrupted operation of a storage device. The storage device includes a non-volatile memory configured to include a plurality of physical storage areas and a controller. The controller calculates the degree of deterioration of each of a plurality of specific physical storage areas by performing an evaluation process of evaluating the plurality of specific physical storage areas part by part over all of the plurality of specific physical storage areas and determines whether to use the corresponding physical storage areas based on the calculated degree of deterioration. In the evaluation process, the controller selects a part of the plurality of specific physical storage areas writes predetermined evaluation data on the physical storage area group, reads the evaluation data and calculates the degree of deterioration based on the read evaluation data.

Abstract: A cache memory comprises a cache controller and a nonvolatile semiconductor memory as a storage medium. The nonvolatile semiconductor memory comprises multiple blocks, which are data erase units, and each block comprises multiple pages, which are data write and read units. The cache controller receives data and attribute information of the data, and, based on the received attribute information and attribute information of the data stored in the multiple blocks, selects a storage-destination block for storing the received data, and writes the received data to a page inside the selected storage-destination block.

Abstract: A semiconductor storage apparatus comprises a memory controller and flash memories which include a plurality of blocks as storage areas. The memory controller is configured to manage a degree of deterioration and read frequency for each of the plurality of blocks. A reliability maintained period is calculated for each storage area based on the degree of deterioration and read frequency for each storage area of a flash memory, and refresh is executed on each storage area in a planned manner based on the calculated reliability maintained period by newly storing the data stored in a block in another block based on an obtained reliability maintained period. The memory controller may also be configured to execute verification on each block and, if the number of failure bits is larger than a predetermined threshold, execute refresh to store data which is stored in a verification target block in another block.

Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.

Abstract: The flash memory controller compresses data in response to a write request. On condition that there is a compression effect with respect to the compressed data, the flash memory controller writes the compressed data to the base area of a physical block of a flash memory. As physical pages assigned to the physical block, the flash memory controller reduces the physical pages assigned to the base area from 102 down to 59, and increases the physical pages assigned to the update area from 26 up to 69. Therefore, it is possible to suppress exhaustion of physical pages which are assigned to the update area, to reduce the number of erases of the physical block, and to consequently prolong device operating life.

Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.

Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.

Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.

Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.