Patents by Inventor Akifumi Suzuki

Akifumi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8898545
    Abstract: A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
  • Publication number: 20140304451
    Abstract: A storage system, which comprises multiple memory cells and a storage controller, wherein the storage controller manages cell mode information, which either directly or indirectly denotes the number of bits to be stored in multiple memory cells. The cell mode information can be changed in accordance with a request from a management system.
    Type: Application
    Filed: December 21, 2011
    Publication date: October 9, 2014
    Applicant: HITACHI, LTD.
    Inventors: Tsukasa Shibayama, Akifumi Suzuki, Nobuhiro Maki, Junji Ogawa, Masayasu Asano
  • Patent number: 8806108
    Abstract: A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Junji Ogawa
  • Publication number: 20140204673
    Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.
    Type: Application
    Filed: March 21, 2014
    Publication date: July 24, 2014
    Applicant: HITACHI, LTD.
    Inventor: Akifumi Suzuki
  • Patent number: 8775723
    Abstract: A storage system is provided with a plurality of nonvolatile semiconductor storage devices (hereafter referred to as semiconductor storage devices) and a storage controller that is coupled to the plurality of semiconductor storage devices and that provides an LU (logical unit) to an upper level apparatus. Each of the semiconductor storage devices is provided with a nonvolatile semiconductor storage medium (hereafter referred to as a semiconductor medium) and a medium controller that is a controller that is coupled to the semiconductor medium.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: July 8, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Akifumi Suzuki
  • Publication number: 20140189203
    Abstract: A cache memory (CM) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The CM comprises a nonvolatile semi-conductor memory (NVM), and provides a logical space to the controller. The controller is configured to partition the logical space into multiple segments and to manage these segments, and to access the CM by specifying a logical address of the logical space. The CM receives the logical address-specified access, and accesses a physical area allocated to a logical area, which belongs to the specified logical address. A first management unit, which is a unit of a segment, is larger than a second management unit, which is a unit of an access performed with respect to the NVM. The capacity of the logical space is larger than the storage capacity of the NVM.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Junji Ogawa, Akira Yamamoto
  • Patent number: 8733991
    Abstract: A vehicle lamp is formed using a light guide body. Thus light with an excellent aesthetic quality can be emitted without increasing the number of components. The structure has a light guide part (6a) formed on a light guide member (6). The light guide part (6a) emits light in an elongated shape by irradiating a first light-emitting diode (9) provided on one end of the light guide part (6a) in the longitudinal direction. A projecting part (6g) projects reward on the rear face of the light guide part (6a), which is the light-emitting face. A light emission suppressing part (6h) is provided on the projection end face of the projecting part (6g) and has a metal film (6f) formed by vapor deposition.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: May 27, 2014
    Assignee: Mitsuba Corporation
    Inventors: Yosuke Fukasawa, Hitoshi Kurihara, Akifumi Suzuki, Atsushi Obata
  • Patent number: 8725936
    Abstract: A storage system has: one or more flash memory chips, each of which has a storage region configured by a plurality of blocks; and a device controller that controls access to data corresponding to the storage regions of the flash memory chips. The device controller manages for each of the blocks the number of determination readings for determining read disturb on the basis of a read request with respect to data of each block from a higher-level device, and, when there is a block for which the number of determination readings becomes equal to or larger than a threshold represented as a standard indicating a predetermined state related to read disturb, transmits, to the higher-level device, notification information that includes information indicating that read disturb of the block enters the predetermined state.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 13, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Oikawa, Akifumi Suzuki, Taichi Yotsumoto
  • Patent number: 8719668
    Abstract: Provided in one embodiment is a nonvolatile storage system having multiple nonvolatile storage media and a controller coupled to the multiple nonvolatile storage media. The controller has a storage area configured to store management information including probability management information denoting error probability information of a unit physical area in a nonvolatile storage medium, and an error correcting circuit configured to carry out coding and decoding by a low density parity check code. The controller, in a data read process, is configured to identify based on management information an error probability, uses the identified error probability to correct the read data using the error correcting circuit.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 6, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akiyoshi Hashimoto, Akifumi Suzuki, Takashi Tsunehiro
  • Patent number: 8681554
    Abstract: A semiconductor storage apparatus stores management information comprising, for each block of a nonvolatile semiconductor memory, information denoting at least one of a recent programming time, which is a time at which data is recently programmed to a block, and a recent erase time, which is a time at which an erase process is recently carried out with respect to a block. The semiconductor storage apparatus (b1) controls a timing at which data is programmed to a block based on at least one of the recent programming time and the recent erase time of this block, and/or (b2) controls a timing at which an erase process is carried out with respect to a block based on the recent programming time of this block.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: March 25, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Akifumi Suzuki
  • Publication number: 20140016341
    Abstract: A turn lamp to be mounted on a door mirror of a vehicle, the turn lamp includes a housing; a light source; and a substrate having a feeder circuit for the light source, wherein: the substrate is placed in the housing such that a plane direction of the substrate faces a horizontal direction when the door mirror is mounted to a vehicle body, and the light source is placed on the substrate such that an irradiation direction of the light source is parallel to the plane direction of the substrate.
    Type: Application
    Filed: March 23, 2012
    Publication date: January 16, 2014
    Applicant: MITSUBA CORPORATION
    Inventors: Yasushi Kawaji, Akifumi Suzuki
  • Publication number: 20130311854
    Abstract: A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Inventors: Takashi Tsunehiro, Akifumi Suzuki, Junji Ogawa
  • Publication number: 20130262749
    Abstract: A storage system has: one or more flash memory chips, each of which has a storage region configured by a plurality of blocks; and a device controller that controls access to data corresponding to the storage regions of the flash memory chips. The device controller manages for each of the blocks the number of determination readings for determining read disturb on the basis of a read request with respect to data of each block from a higher-level device, and, when there is a block for which the number of determination readings becomes equal to or larger than a threshold represented as a standard indicating a predetermined state related to read disturb, transmits, to the higher-level device, notification information that includes information indicating that read disturb of the block enters the predetermined state.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Yoshihiro Oikawa, Akifumi Suzuki, Taichi Yotsumoto
  • Publication number: 20130238836
    Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.
    Type: Application
    Filed: March 6, 2012
    Publication date: September 12, 2013
    Inventors: Akifumi Suzuki, Takashi Tsunehiro
  • Patent number: 8456292
    Abstract: A door mirror includes a turn signal lamp for indicating a traveling direction; a foot lamp; and a housing that houses the turn signal lamp and the foot lamp, wherein the turn signal lamp and the foot lamp are provided in the housing such that the turn signal lamp and the foot lamp are provided with outer lenses lying adjacent to each other such that light based on a turning on of one lamp is guided to an outer lens of the other lamp.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: June 4, 2013
    Assignees: Mitsuba Corporation, Toyota Jidosha Kabushiki Kaisha
    Inventors: Yosuke Fukasawa, Akifumi Suzuki, Tatsuya Sugamoto
  • Publication number: 20130132641
    Abstract: A storage system is provided with a plurality of nonvolatile semiconductor storage devices (hereafter referred to as semiconductor storage devices) and a storage controller that is coupled to the plurality of semiconductor storage devices and that provides an LU (logical unit) to an upper level apparatus. Each of the semiconductor storage devices is provided with a nonvolatile semiconductor storage medium (hereafter referred to as a semiconductor medium) and a medium controller that is a controller that is coupled to the semiconductor medium.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Inventor: Akifumi Suzuki
  • Publication number: 20130111299
    Abstract: A nonvolatile storage system has multiple nonvolatile storage media and a controller coupled to the multiple nonvolatile storage media. The controller has a storage area for storing management information including probability management information denoting error probability information of a unit physical area in a nonvolatile storage medium, and an error correcting circuit for carrying out coding and decoding by a low density parity check code. An error probability is a probability that data within the unit physical area is incorrect, and is a prior probability, which is the probability of prior to this data having been read.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Inventors: Akiyoshi Hashimoto, Akifumi Suzuki, Takashi Tsunehiro
  • Publication number: 20130051144
    Abstract: A semiconductor storage apparatus stores management information comprising, for each block of a nonvolatile semiconductor memory, information denoting at least one of a recent programming time, which is a time at which data is recently programmed to a block, and a recent erase time, which is a time at which an erase process is recently carried out with respect to a block. The semiconductor storage apparatus (b1) controls a timing at which data is programmed to a block based on at least one of the recent programming time and the recent erase time of this block, and/or (b2) controls a timing at which an erase process is carried out with respect to a block based on the recent programming time of this block.
    Type: Application
    Filed: August 29, 2011
    Publication date: February 28, 2013
    Applicant: HITACHI, LTD.
    Inventor: Akifumi Suzuki
  • Publication number: 20120317334
    Abstract: A semiconductor storage apparatus including a flash memory which provides a storage area, and a memory controller which controls the reading and writing of data from and to the flash memory, wherein the storage area of the flash memory is configured from a plurality of write areas, and wherein the memory controller divides the data into a size corresponding to the write area, and changes the starting location of writing the data each time the divided data is written into the write area.
    Type: Application
    Filed: June 7, 2011
    Publication date: December 13, 2012
    Applicant: HITACHI, LTD.
    Inventors: Akifumi Suzuki, Junji Ogawa
  • Publication number: 20120278533
    Abstract: A reliability maintained period is calculated for each storage area based on the degree of deterioration and read frequency for each storage area of a flash memory, and refresh is executed on each storage area in a planned manner based on the calculated reliability maintained period. A semiconductor storage apparatus 100A is configured so that flash memories 120 to 128 and a memory controller 110 are connected and the flash memories 120 to 128 include a plurality of blocks as storage areas; and the memory controller 110 manages the degree of deterioration and read frequency of the blocks for each of the plurality of blocks, obtains a reliability maintained period of data stored in the block based on the managed degree of deterioration and read frequency of the block, and executes refresh for correcting failure bits of the relevant data by newly storing the data stored in the block in another block based on the obtained reliability maintained period.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 1, 2012
    Inventors: Akifumi Suzuki, Takashi Tsunehiro