Patents by Inventor Akiharu Miyanaga

Akiharu Miyanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7769226
    Abstract: A color image of an inspection object is taken by an imaging means capable of taking a color image to obtain color information of an RGB color space. A gray-scale image of a color component of the RGB color space or another color space is generated, and the inspection object is detected by a pattern recognition technique. Alternatively, a binary image is generated from the generated gray-scale image, and the inspection object is detected by performing pattern recognition on the binary image. Color data of a pixel occupied by the detected inspection object is compared with color data of a non-defective inspection object which is previously prepared to judge whether or not the inspection object is defective. In addition, this judgment result is reflected in another manufacturing step through a network and product quality is improved.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: August 3, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Teppei Oguni, Tatsuji Nishijima, Akiharu Miyanaga
  • Patent number: 7749819
    Abstract: It is an object to obtain a crystalline silicon film having preferable characteristics for a thin film transistor. A crystalline silicon film having improved crystallinity is obtained by the following steps: forming a silicon nitride film substantially in contact with an amorphous silicon film on glass substrate; introducing a catalyst element such as nickel; performing an annealing treatment at a temperature of 500 to 600° C. for crystallization; and further irradiating it with a laser light, thereby a crystalline silicon film having improved crystallinity can be obtained. By using the crystalline silicon film thus obtained, a semiconductor device such as a TFT having improved characteristic can be obtained.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: July 6, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Hongyong Zhang, Naoaki Yamaguchi
  • Publication number: 20100127261
    Abstract: The thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode, an amorphous semiconductor layer over the gate insulating layer, a semiconductor layer including an impurity element imparting one conductivity type over the amorphous semiconductor layer. The amorphous semiconductor layer comprises an NH radical. Defects of the amorphous semiconductor layer are reduced by cross-linking dangling bonds with the NH radical in the amorphous semiconductor layer.
    Type: Application
    Filed: May 15, 2009
    Publication date: May 27, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Koji DAIRIKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Takuya HIROHASHI
  • Publication number: 20100123130
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Application
    Filed: November 16, 2009
    Publication date: May 20, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kengo AKIMOTO, Junichiro SAKATA, Takuya HIROHASHI, Masahiro TAKAHASHI, Hideyuki KISHIDA, Akiharu MIYANAGA
  • Patent number: 7700421
    Abstract: A semiconductor device using a crystalline semiconductor film is manufactured. The crystalline semiconductor film is formed by providing an amorphous silicon film with a catalyst metal for promoting a crystallization thereof and then heated for performing a thermal crystallization, following which the crystallized film is further exposed to a laser light for improving the crystallinity. The concentration of the catalyst metal in the semiconductor film and the location of the region to be added with the catalyst metal are so selected in order that a desired crystallinity and a desired crystal structure such as a vertical crystal growth or lateral crystal growth can be obtained. Further, active elements and driver elements of a circuit substrate for an active matrix type liquid crystal device are formed by such semiconductor devices having a desired crystallinity and crystal structure respectively.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: April 20, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Hisashi Ohtani, Yasuhiko Takemura
  • Patent number: 7687855
    Abstract: To provide a semiconductor device that can effectively suppress the short channel effect without deterioration of carrier migration, an impurity ion is added from a direction of the <110> axis with respect to a silicon substrate on forming a punch through stopper under the gate electrode. In this invention, because the addition of the impurity is conducted by utilizing the principal of channeling, the impurity can be added with a small amount of scattering suppressing damage on the surface of the silicon substrate. A channel forming region having an extremely small impurity concentration and substantially no crystallinity disorder is formed.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: March 30, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Nobuo Kubo
  • Patent number: 7671425
    Abstract: In a semiconductor device, pining regions 105 are disposed along the junction portion of a drain region 102 and a channel forming region 106 locally in a channel width direction. With this structure, because the spread of a depletion layer from a drain side is restrained by the pining regions 105, a short-channel effect can be restrained effectively. Also, because a passage through which carriers move is ensured, high mobility can be maintained.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: March 2, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Nobuo Kubo
  • Publication number: 20100041247
    Abstract: The object of the present invention is to solve problems of treatment time when using an SLS method or continuous-oscillation laser. An indispensable portion is scanned with a laser beam in order to crystallize a semiconductor film by driving a laser and so on in accordance with the positions of islands instead of scanning and irradiating the whole semiconductor film. The present invention makes it possible to omit the time for irradiating a portion to be removed through patterning after crystallizing the semiconductor film with a laser beam and greatly shorten the treatment time for one substrate.
    Type: Application
    Filed: September 3, 2009
    Publication date: February 18, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akiharu MIYANAGA, Kyouichi MUKAO
  • Publication number: 20100032667
    Abstract: One of the objects of the present invention is to provide a thin film transistor using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance between the oxide semiconductor layer and a source and drain electrodes is reduced, and to provide a method for manufacturing the thin film transistor. An ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the IGZO semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100032665
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 11, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100025679
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20100025676
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: July 29, 2009
    Publication date: February 4, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20090267068
    Abstract: The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 29, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Koji DAIRIKI, Hidekazu MIYAIRI, Toshiyuki ISA, Akiharu MIYANAGA, Takuya HIROHASHI, Shunpei YAMAZAKI, Takeyoshi WATABE
  • Patent number: 7588974
    Abstract: The object of the present invention is to solve problems of treatment time when using an SLS method or continuous-oscillation laser. An indispensable portion is scanned with a laser beam in order to crystallize a semiconductor film by driving a laser and so on in accordance with the positions of islands instead of scanning and irradiating the whole semiconductor film. The present invention makes it possible to omit the time for irradiating a portion to be removed through patterning after crystallizing the semiconductor film with a laser beam and greatly shorten the treatment time for one substrate.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: September 15, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Kyouichi Mukao
  • Patent number: 7553716
    Abstract: A little amount of nickel is introduced into an amorphous silicon film formed on a glass substrate to crystallize the amorphous silicon film by heating. In this situation, nickel elements remain in a crystallized silicon film. An amorphous silicon film is formed on the surface of the crystallized silicon film and then subjected to a heat treatment. With this heat treatment, the nickel elements are diffused in the amorphous silicon film, thereby being capable of lowering the concentration of nickel in the crystallized silicon film.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: June 30, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto
  • Publication number: 20090081849
    Abstract: To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H3+ ions by an ion doping apparatus. H3+ ions accelerated by high voltage are separated to be three H+ ions at a semiconductor wafer surface, and the H+ ions cannot enter deeply. Therefore, H+ ions are added into a shallower region in the semiconductor wafer at a higher concentration than the case of using a conventional ion implantation method.
    Type: Application
    Filed: September 15, 2008
    Publication date: March 26, 2009
    Applicant: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Ko Inada, Yuji Iwaki
  • Publication number: 20090075460
    Abstract: A process for fabricating a semiconductor device comprising the steps of introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.
    Type: Application
    Filed: November 12, 2008
    Publication date: March 19, 2009
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi OHTANI, Takeshi FUKUNAGA, Akiharu MIYANAGA
  • Publication number: 20090035923
    Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.
    Type: Application
    Filed: July 15, 2008
    Publication date: February 5, 2009
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Akiharu Miyanaga, Takeshi Fukunaga, Hongyong Zhang
  • Patent number: 7470575
    Abstract: A process for fabricating a semiconductor device including the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: December 30, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Takeshi Fukunaga, Akiharu Miyanaga
  • Publication number: 20080286950
    Abstract: A semiconductor device using a crystalline semiconductor film is manufactured. The crystalline semiconductor film is formed by providing an amorphous silicon film with a catalyst metal for promoting a crystallization thereof and then heated for performing a thermal crystallization, following which the crystallized film is further exposed to a laser light for improving the crystallinity. The concentration of the catalyst metal in the semiconductor film and the location of the region to be added with the catalyst metal are so selected in order that a desired crystallinity and a desired crystal structure such as a vertical crystal growth or lateral crystal growth can be obtained. Further, active elements and driver elements of a circuit substrate for an active matrix type liquid crystal device are formed by such semiconductor devices having a desired crystallinity and crystal structure respectively.
    Type: Application
    Filed: July 18, 2008
    Publication date: November 20, 2008
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Akiharu MIYANAGA, Hisashi OHTANI, Yasuhiko TAKEMURA