Patents by Inventor Akiharu Miyanaga

Akiharu Miyanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10422937
    Abstract: To provide a wavelength converting member in which the occurrence of blackening can be suppressed compared to the prior art; and a light emitting device, a light emitting element, a light source unit, and a display device using the wavelength converting member. The wavelength converting member includes: a receptacle including a light entrance plane and a light exit plane opposite to the light entrance plane and provided with a receiving space inside the light entrance plane and the light exit plane; and a wavelength conversion layer having quantum dots that is placed in the receiving space. The distance between the light entrance plane and the wavelength conversion layer is longer than the distance between the light exit plane and the wavelength conversion layer.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: September 24, 2019
    Assignee: NS MATERIALS INC.
    Inventors: Akiharu Miyanaga, Shingo Kokudo, Eiichi Kanaumi, Tetsuji Ito, Yoshikazu Nageno
  • Patent number: 10418491
    Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 17, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 10403763
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Patent number: 10355136
    Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film. The spin density of the gate insulating film or the protective film measured by electron spin resonance spectroscopy is lower than 1×1018 spins/cm3, preferably higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 16, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Motoki Nakashima, Masahiro Takahashi, Shunsuke Adachi, Takuya Hirohashi
  • Publication number: 20190157516
    Abstract: A resin molded product is provided and capable of increasing a degree of freedom of a shape compared to prior arts, further provided with increased durability against environmental changes and improved reliability, a manufacturing method thereof, and a wavelength conversion member and an illumination member. The resin molded product is implemented by molding resin in which quantum dots are dispersed. The resin preferably contains a dispersant composed of metal soap. For example, a wavelength conversion bar (fluorescent bar) interposed between a light-emitting device such as an LED and a light-guiding board is molded using quantum-dot-containing resin.
    Type: Application
    Filed: January 24, 2019
    Publication date: May 23, 2019
    Applicant: NS MATERIALS INC.
    Inventors: Kazuyuki YAMASHITA, Eiichi KANAUMI, Akiharu MIYANAGA
  • Publication number: 20190157461
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 10290742
    Abstract: It is an object to provide a semiconductor device typified by a display device having a favorable display quality, in which parasitic resistance generated in a connection portion between a semiconductor layer and an electrode is suppressed and an adverse effect such as voltage drop, a defect in signal wiring to a pixel, a defect in grayscale, and the like due to wiring resistance are prevented. In order to achieve the above object, a semiconductor device according to the present invention may have a structure where a wiring with low resistance is connected to a thin film transistor in which a source electrode and a drain electrode that include metal with high oxygen affinity are connected to an oxide semiconductor layer with a suppressed impurity concentration. In addition, the thin film transistor including the oxide semiconductor may be surrounded by insulating films to be sealed.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Yasuo Nakamura, Junpei Sugao, Hideki Uochi
  • Patent number: 10266769
    Abstract: To provide a quantum dot and manufacturing method of the dot particularly capable of reducing organic residues adhering to the quantum dot surface and of suppressing the black discoloration occurrence of a layer including the quantum dot positioned immediately above a light emitting device, and a compact, sheet member, wavelength conversion member and light emitting apparatus with high luminous efficiency using the quantum dot, a quantum dot of the present invention has a core portion including a semiconductor particle, and a shell portion with which the surface of the core portion is coated, and is characterized in that a weight reduction up to 490° C. is within 75% in a TG-DTA profile. Further, the quantum dot of the invention is characterized in that oleylamine (OLA) is not observed in GC-MS qualitative analysis at 350° C.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: April 23, 2019
    Assignee: NS MATERIALS INC.
    Inventors: Akiharu Miyanaga, Eiichi Kanaumi, Yoshikazu Nageno
  • Patent number: 10256291
    Abstract: An object is to provide a method for manufacturing a highly reliable semiconductor device including a transistor with stable electric characteristics. A method for manufacturing a semiconductor device includes the steps of: forming a gate electrode over a substrate having an insulating surface; forming a gate insulating film over the gate electrode; forming an oxide semiconductor film over the gate insulating film; irradiating the oxide semiconductor film with an electromagnetic wave such as a microwave or a high frequency; forming a source electrode and a drain electrode over the oxide semiconductor film irradiated with the electromagnetic wave; and forming an oxide insulating film, which is in contact with part of the oxide semiconductor film, over the gate insulating film, the oxide semiconductor film, the source electrode, and the drain electrode.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akiharu Miyanaga
  • Publication number: 20190010396
    Abstract: A quantum dot has a property that, when subjected to a GC-MS qualitative analysis at 350° C., octadecene (ODE) is present while oleylamine (OLA) is absent. A light emitting apparatus has a fluorescent layer covering and disposed immediately above a light emitting side of a light emitting device. The fluorescent layer, which is disposed immediately above the light emitting device, is formed of a resin with quantum dots dispersed therein. Deteriorations of light emission intensities at respective RGB peak wavelengths of the light emitting device after light emission for 1000 hours at 85° C. are all within 30% of a light emission intensity of the light emitting device before the light emission. Black discoloration caused by the deteriorations of the light emission intensities at the respective RGB peak wavelengths of the light emitting device does not occur in the resin.
    Type: Application
    Filed: September 14, 2018
    Publication date: January 10, 2019
    Applicant: NS MATERIALS INC.
    Inventors: Akiharu MIYANAGA, Eiichi KANAUMI, Yoshikazu NAGENO
  • Publication number: 20180356070
    Abstract: To provide a wavelength conversion member, molded body, wavelength conversion apparatus, sheet member, light emitting apparatus, light guide apparatus and display apparatus particularly capable of suppressing the black discoloration occurrence of a resin layer positioned immediately above a light emitting device as compared with conventional techniques, the present invention provides an LED apparatus having a storage portion, an LED chip disposed inside the storage portion, and a resin layer filled inside the storage portion, the resin layer is comprised by having a first resin layer on the side close to an LED device, and a second resin layer on the side far from the LED device, a light scattering agent is included in at least the first resin layer, and quantum dots are not included in the first resin layer and are included in the second resin layer.
    Type: Application
    Filed: July 25, 2018
    Publication date: December 13, 2018
    Applicant: NS MATERIALS INC.
    Inventors: Akiharu MIYANAGA, Eiichi KANAUMI
  • Publication number: 20180350998
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 6, 2018
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Akiharu MIYANAGA, Junpei SUGAO, Hideki UOCHI, Yasuo NAKAMURA
  • Patent number: 10141450
    Abstract: An object is to provide a thin film transistor having favorable electric characteristics and a semiconductor device including the thin film transistor as a switching element. The thin film transistor includes a gate electrode formed over an insulating surface, a gate insulating film over the gate electrode, an oxide semiconductor film which overlaps with the gate electrode over the gate insulating film and which includes a layer where the concentration of one or a plurality of metals contained in the oxide semiconductor is higher than that in other regions, a pair of metal oxide films formed over the oxide semiconductor film and in contact with the layer, and a source electrode and a drain electrode in contact with the metal oxide films. The metal oxide films are formed by oxidation of a metal contained in the source electrode and the drain electrode.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Junichiro Sakata, Masayuki Sakakura, Masahiro Takahashi, Hideyuki Kishida, Shunpei Yamazaki
  • Patent number: 10115831
    Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Ryosuke Watanabe, Junichiro Sakata, Kengo Akimoto, Akiharu Miyanaga, Takuya Hirohashi, Hideyuki Kishida
  • Publication number: 20180308989
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Application
    Filed: June 28, 2018
    Publication date: October 25, 2018
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Kengo AKIMOTO, Hiroki OHARA, Tatsuya HONDA, Takatsugu OMATA, Yusuke NONAKA, Masahiro TAKAHASHI, Akiharu MIYANAGA
  • Patent number: 10101008
    Abstract: To provide a wavelength conversion member, molded body, wavelength conversion apparatus, sheet member, light emitting apparatus, light guide apparatus and display apparatus particularly capable of suppressing the black discoloration occurrence of a resin layer positioned immediately above a light emitting device as compared with conventional techniques, the present invention provides an LED apparatus having a storage portion, an LED chip disposed inside the storage portion, and a resin layer filled inside the storage portion, the resin layer is comprised by having a first resin layer on the side close to an LED device, and a second resin layer on the side far from the LED device, a light scattering agent is included in at least the first resin layer, and quantum dots are not included in the first resin layer and are included in the second resin layer.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: October 16, 2018
    Assignee: NS MATERIALS INC.
    Inventors: Akiharu Miyanaga, Eiichi Kanaumi
  • Patent number: 10103277
    Abstract: A method comprising a step of forming an oxide semiconductor film over a substrate by a sputtering method while heating the substrate at a temperature of higher than 200° C. and lower than or equal to 400° C. is provided. The oxide semiconductor film comprises a crystalline region and is in a non-single-crystal state. The step of forming the oxide semiconductor film is performed by using a sputtering target comprising indium, gallium, zinc and oxygen and a sputtering gas comprising at least one of a rare gas and oxygen.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: October 16, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Publication number: 20180226510
    Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 10043915
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Publication number: 20180175210
    Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film. The spin density of the gate insulating film or the protective film measured by electron spin resonance spectroscopy is lower than 1×1018 spins/cm3, preferably higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Akiharu MIYANAGA, Yasuharu HOSAKA, Toshimitsu OBONAI, Junichi KOEZUKA, Motoki NAKASHIMA, Masahiro TAKAHASHI, Shunsuke ADACHI, Takuya HIROHASHI