Patents by Inventor Akiharu Miyanaga

Akiharu Miyanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9748401
    Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: ?1 and ?2, ?1<?2 is satisfied, and ?2 is 300 seconds or less. In addition, a semiconductor device including the transistor is manufactured.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 29, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Takayuki Inoue, Suzunosuke Hiraishi, Erumu Kikuchi, Hiromichi Godo, Shuhei Yoshitomi, Koki Inoue, Akiharu Miyanaga, Shunpei Yamazaki
  • Publication number: 20170236943
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20170222095
    Abstract: It is an object of the present invention to provide a resin molded product capable of increasing a degree of freedom of a shape compared to prior arts, further provided with increased durability against environmental changes and improved reliability, a manufacturing method thereof, and a wavelength conversion member and an illumination member. The present invention is implemented by molding resin in which quantum dots are dispersed. The resin preferably contains a dispersant composed of metal soap. For example, a wavelength conversion bar (fluorescent bar) (3) interposed between a light-emitting device (1) such as an LED and a light-guiding board (2) is molded using quantum-dot-containing resin of the present invention.
    Type: Application
    Filed: July 31, 2015
    Publication date: August 3, 2017
    Applicant: NS MATERIALS INC.
    Inventors: Kazuyuki YAMASHITA, Eiichi KANAUMI, Akiharu MIYANAGA
  • Patent number: 9711655
    Abstract: A semiconductor device comprising a first metal oxide film, an oxide semiconductor film, a second metal oxide film, a gate insulating film, and a gate electrode is provided. The oxide semiconductor film comprises an In—Ga—Zn—O-based metal oxide. The second metal oxide film comprises a Ga—Zn—O-based metal oxide. An amount of substance of zinc oxide with respect to gallium oxide is lower than 50% in the Ga—Zn—O-based metal oxide.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 18, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Publication number: 20170162700
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Akiharu MIYANAGA, Junpei SUGAO, Hideki UOCHI, Yasuo NAKAMURA
  • Publication number: 20170162719
    Abstract: An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.
    Type: Application
    Filed: February 23, 2017
    Publication date: June 8, 2017
    Inventors: Shunpei YAMAZAKI, Akiharu MIYANAGA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Junichiro SAKATA
  • Patent number: 9666719
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: May 30, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20170137710
    Abstract: To provide a quantum dot and manufacturing method of the dot particularly capable of reducing organic residues adhering to the quantum dot surface and of suppressing the black discoloration occurrence of a layer including the quantum dot positioned immediately above a light emitting device, and a compact, sheet member, wavelength conversion member and light emitting apparatus with high luminous efficiency using the quantum dot, a quantum dot of the present invention has a core portion including a semiconductor particle, and a shell portion with which the surface of the core portion is coated, and is characterized in that a weight reduction up to 490° C. is within 75% in a TG-DTA profile. Further, the quantum dot of the invention is characterized in that oleylamine (OLA) is not observed in GC-MS qualitative analysis at 350° C.
    Type: Application
    Filed: April 3, 2015
    Publication date: May 18, 2017
    Applicant: NS MATERIALS INC.
    Inventors: Akiharu MIYANAGA, Eiichi KANAUMI, Yoshikazu NAGENO
  • Publication number: 20170122527
    Abstract: To provide a wavelength conversion member, compact, wavelength conversion apparatus, sheet member, light emitting apparatus, light guide apparatus and display apparatus particularly capable of suppressing the black discoloration occurrence of a resin layer positioned immediately above a light emitting device as compared with conventional techniques, the present invention provides an LED apparatus having a storage portion, an LED chip disposed inside the storage portion, and a resin layer filled inside the storage portion, the resin layer is comprised by having a first resin layer on the side close to an LED device, and a second resin layer on the side far from the LED device, a light scattering agent is included in at least the first resin layer, and quantum dots are not included in the first resin layer and are included in the second resin layer.
    Type: Application
    Filed: April 3, 2015
    Publication date: May 4, 2017
    Applicant: NS MATERIALS INC.
    Inventors: Akiharu MIYANAGA, Eiichi KANAUMI
  • Patent number: 9627198
    Abstract: An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 18, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Masahiro Takahashi, Hideyuki Kishida, Junichiro Sakata
  • Patent number: 9601633
    Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time ?1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Inoue, Masashi Tsubuku, Suzunosuke Hiraishi, Junichiro Sakata, Erumu Kikuchi, Hiromichi Godo, Akiharu Miyanaga, Shunpei Yamazaki
  • Patent number: 9601635
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Publication number: 20170040458
    Abstract: An object is to provide a thin film transistor having favorable electric characteristics and a semiconductor device including the thin film transistor as a switching element. The thin film transistor includes a gate electrode formed over an insulating surface, a gate insulating film over the gate electrode, an oxide semiconductor film which overlaps with the gate electrode over the gate insulating film and which includes a layer where the concentration of one or a plurality of metals contained in the oxide semiconductor is higher than that in other regions, a pair of metal oxide films formed over the oxide semiconductor film and in contact with the layer, and a source electrode and a drain electrode in contact with the metal oxide films. The metal oxide films are formed by oxidation of a metal contained in the source electrode and the drain electrode.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 9, 2017
    Inventors: Akiharu MIYANAGA, Junichiro SAKATA, Masayuki SAKAKURA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Shunpei YAMAZAKI
  • Publication number: 20160380111
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Akiharu MIYANAGA, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Patent number: 9530872
    Abstract: An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: December 27, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Akiharu Miyanaga, Masayuki Sakakura, Junichi Koezuka, Tetsunori Maruyama, Yuki Imoto
  • Patent number: 9530893
    Abstract: The field of an oxide semiconductor has been attracted attention in recent years. Therefore, the correlation between electric characteristics of a transistor including an oxide semiconductor layer and physical properties of the oxide semiconductor layer has not been clear yet. Thus, a first object is to improve electric characteristics of the transistor by control of physical properties of the oxide semiconductor layer. A semiconductor device including at least a gate electrode, an oxide semiconductor layer, and a gate insulating layer sandwiched between the gate electrode and the oxide semiconductor layer, where the oxide semiconductor layer has the relative permittivity of equal to or higher than 13 (or equal to or higher than 14), is provided.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 27, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Tatsuya Honda
  • Patent number: 9520288
    Abstract: It is an object to provide a thin film transistor having favorable electric characteristics and high reliability and a semiconductor device which includes the thin film transistor as a switching element. An In—Ga—Zn—O-based film having an incubation state that shows an electron diffraction pattern, which is different from a conventionally known amorphous state where a halo shape pattern appears and from a conventionally known crystal state where a spot appears clearly, is formed. The In—Ga—Zn—O-based film having an incubation state is used for a channel formation region of a channel etched thin film transistor.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: December 13, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akiharu Miyanaga, Junichiro Sakata, Masayuki Sakakura, Shunpei Yamazaki
  • Publication number: 20160351721
    Abstract: In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The semiconductor device includes a gate electrode over an insulating surface; an oxide semiconductor film overlapping with the gate electrode; a gate insulating film that is between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film; a protective film in contact with a surface of the oxide semiconductor film that is an opposite side of a surface in contact with the gate insulating film; and a pair of electrodes in contact with the oxide semiconductor film. The spin density of the gate insulating film or the protective film measured by electron spin resonance spectroscopy is lower than 1×1018 spins/cm3, preferably higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.
    Type: Application
    Filed: August 10, 2016
    Publication date: December 1, 2016
    Inventors: Akiharu MIYANAGA, Yasuharu HOSAKA, Toshimitsu OBONAI, Junichi KOEZUKA, Motoki NAKASHIMA, Masahiro TAKAHASHI, Shunsuke ADACHI, Takuya HIROHASHI
  • Publication number: 20160336456
    Abstract: In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.
    Type: Application
    Filed: July 27, 2016
    Publication date: November 17, 2016
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 9496406
    Abstract: An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: November 15, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi