Abstract: A metal line 731 is formed in a linear area S of an insulative substrate 720, and moreover a metal line 732 is formed generally parallel to the metal line 731 with a specified distance thereto. The metal line 731 is connected to an n-type semiconductor core 701 of bar-like structure light-emitting elements 710A to 710D, and the metal line 732 is connected to a p-type semiconductor layer 702. By dividing the insulative substrate 720 into a plurality of divisional substrates, a plurality of light-emitting devices in each of which a plurality of bar-like structure light-emitting elements 710 are placed on the divisional substrates are formed.

Abstract: In a light emitting device, one hundred or more bar-like structured light emitting elements (210) each having a light emitting area of 2,500? ?m2 or less are placed on a mounting surface of one insulating substrate (200), so that the light emitting device fulfills little variation in luminance, long life, and high efficiency by dispersion of light emission with suppression of increase in temperatures in light emitting operations.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: An object of the present invention is to implement a method for aligning microscopic structures in desired locations and in a desired direction, in order to align microscopic structures, such as nanostructures, with high precision. The method includes a substrate forming step of forming three electrodes to which independent potentials can be applied, a microscopic structure liquid applying step of applying a liquid in which microscopic structures are dispersed to the insulating substrate, and a microscopic structure aligning step of applying respective voltages to the three electrodes to align the microscopic structures in locations defined by the electrodes.

Abstract: Methods, systems, and apparatuses for nanowire deposition are provided. A deposition system includes an enclosed flow channel, an inlet port, and an electrical signal source. The inlet port provides a suspension that includes nanowires into the channel. The electrical signal source is coupled to an electrode pair in the channel to generate an electric field to associate at least one nanowire from the suspension with the electrode pair. The deposition system may include various further features, including being configured to receive multiple solution types, having various electrode geometries, having a rotatable flow channel, having additional electrical conductors, and further aspects.

Abstract: An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano wires having sizes differing depending on types of nano wire element. With this, it is possible to dramatically improve a function of the integrated circuit device, as compared with an integrated circuit device including a substrate on which one type of nano wire element is provided.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: To provide a semiconductor storage unit that has a simple structure requiring only a small number of processes to produce, and is provided with a gate insulating film having a memory function. The semiconductor storage unit has a semiconductor layer, two diffusion layer regions forming a source region and a drain region, which are formed on the semiconductor layer, a channel region fixed between the two diffusion layer regions, a gate insulating film that is formed on the channel region, and made of a silicon oxide film containing carbon atoms of 0.1 to 5.0 atomic percent, and a gate electrode formed on the gate insulating film.

Abstract: To facilitate electrode connections and achieve a high light emitting efficiency, a rod-like light-emitting device includes a semiconductor core of a first conductivity type having a rod shape, and a semiconductor layer of a second conductivity type formed to cover the semiconductor core. The outer peripheral surface of part of the semiconductor core is exposed.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: In a light emitting device, a P-type first region (506) and a P-type third region (508) are placed on both sides of an N-type second region (507) of a rod-like light emitting element (505). Therefore, even if connection of the first, third regions (506, 508) of the rod-like light emitting element (505) relative to the first, third electrodes (1, 3) is reversed, a diode polarity relative to the first, third electrodes (501, 503) is not reversed, making it possible to effectuate normal light emission. Thus, a connection of the first, third regions (506, 508) relative to the first, third electrodes (501, 503) may be reversed during a manufacturing process, making it unnecessary to provide marks or configurations for discrimination of orientation of the rod-like light emitting element (505), so that the manufacturing process can be simplified and manufacturing cost can be cut down.

Abstract: With reference to a direction perpendicular to a direction of forming electrodes to which a voltage can be applied, fine structures are each arranged within ±5 degrees at a substantially even interval, and a semiconductor element is formed by using the fine structures. On an insulating substrate, at least two electrodes are arranged at a predetermined interval, and there are formed one or more fine structure arranging regions, each of which is formed by a unit of the two electrodes. A semiconductor element electrode is made in contact with the plurality of the fine structures, each having two ends in contact with the two electrodes and a length in a longitudinal direction of a nano order to a micron order, and arranged within ±5 degrees with reference to the direction perpendicular to the direction of forming the electrodes.

Abstract: The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block is provided with an input/output circuit. A transmission line and a branch line connect the input/output circuits so that information can be exchanged through the input/output circuits between one basic circuit block and another basic circuit block. The memory in each basic circuit block or in each input/output circuit can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.

Abstract: A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body has a charge storage insulator and a charge retention insulator positioned between the charge storage insulator and the semiconductor layer, and doubles as a gate insulating film. The charge retention insulator contains such impurity atoms (phosphorus) as would cause an intrinsic semiconductor to be of the second conductivity type.

Abstract: The present invention provides a semiconductor storage device having: a first conductivity type region formed in a semiconductor layer; a second conductivity type region formed in the semiconductor layer in contact with the first conductivity type region; a memory functional element disposed on the semiconductor layer across the boundary of the first and second conductivity type regions; and an electrode provided in contact with the memory functional element and on the first conductivity type region via an insulation film, and a portable electronic apparatus comprising the semiconductor storage device. The present invention can fully cope with scale-down and high-integration by constituting a selectable memory cell substantially of one device.

Abstract: A semiconductor storage device has memory function bodies (261, 262) having a function to retain electric charges, which are formed on opposite sides of a single gate electrode (217) provided on a semiconductor layer (211) with a gate insulation film (214) disposed therebetween. Each memory function body includes a charge retention film (242) having a charge storage region (250). The charge storage regions (250) exist over part of the channel region (273) and part of diffusion regions (212, 213) on both sides of the channel region. Because the memory function bodies are formed on both sides of the gate electrode, independently of the gate insulation film, 2-bit operations are possible. Because the memory function bodies are separated from each other by the gate electrode, interference during rewrite operation is effectively suppressed. Also, short-channel effect is suppressed through thinning of the gate insulation film. Miniaturization of memory elements is thus facilitated.

Abstract: A memory element having a large memory window and a high reliability is provided at low cost by performing high speed write and erase operations at a relatively low voltage and suppressing rewrite degradation. A memory element includes a semiconductor layer arranged on an insulating substrate, a first diffusion layer region and a second diffusion layer region having a conductivity type of P-type, a charge accumulating film for covering a channel region between the first diffusion layer region and the second diffusion layer region and being injected with charges from the channel region, and a gate electrode positioned on a side opposite to the channel region with the charge accumulating film in between.

Abstract: An object of the present invention is to implement a method for aligning microscopic structures in desired locations and in a desired direction, in order to align microscopic structures, such as nanostructures, with high precision. The method includes a substrate forming step of forming three electrodes to which independent potentials can be applied, a microscopic structure liquid applying step of applying a liquid in which microscopic structures are dispersed to the insulating substrate, and a microscopic structure aligning step of applying respective voltages to the three electrodes to align the microscopic structures in locations defined by the electrodes.

Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Abstract: A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.