Abstract: A semiconductor memory device includes a memory cell array in which plural memory cells are arranged, a memory operation circuit, connected to the memory cell array, for executing a memory operation on the memory cell array, and a command controller, connected to the memory operation circuit, for receiving a command from the outside and generating a predetermined control signal to the memory operation circuit on the basis of the received command to control execution of the memory operation by the memory operation circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A semiconductor storage device has a variable-stage charge pump, and a memory cell array to which an output from an output line of the variable-stage charge pump is fed. In the variable-stage charge pump, first and second charge pumps are connected in parallel between a common input bus and a common output bus. A first n-channel MOSFET is provided on a line connecting an output terminal of the first charge pump and the common output bus, and another n-channel MOSFET is provided on a line connecting the second charge pump and the common output bus. First switches are provided between the output terminal of the first charge pump and the first n-channel MOSFET, and between the input terminal of the second charge pump and the second switch. A second switch is provided on a line connecting an input terminal of the second charge pump and the common input bus.

Abstract: A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell.

Abstract: A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.

Abstract: A semiconductor memory device has a malfunction prevention device and a nonvolatile memory. The nonvolatile memory is a memory cell including: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed below the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having a function of retaining charges.

Abstract: While a memory section (1) is in standby mode, a power supply/interruption circuit (2) supplies electric power to a memory section (1) only during periods in which a refresh operation is performed in synchronization with a timing of the refresh operation generated by the clock circuit (3), and interrupts power supply to the memory section (1) during periods in which the refresh operation is not performed. Thus, power consumption of the memory section that performs the refresh operations is suppressed, by which a power consumption reduction of the semiconductor storage device is realized.

Abstract: There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

Abstract: A semiconductor storage device wherein storage of two bits is implemented in one transistor and that can be further minaturized is provided. Two charge holding portions, one on each sidewall of the gate electrode, are formed so as to be independent of the gate insulating film. Thereby, the memory function carried out by the charge holding portions and the transistor operation function carried out by the gate insulating film are separated. The two charge holding portions, formed on opposite sides of the gate electrode, are separated by the gate electrode and, therefore, interference at the time of rewriting can be effectively suppressed. Accordingly, a semiconductor storage device wherein storage of two bits is implemented in one transistor and that is minaturized is provided.

Abstract: A semiconductor storage device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a single gate electrode formed on the gate insulating film, two charge holding portions formed on both sides of the gate electrode, source/drain regions respectively corresponding to the charge holding portions, and a channel region disposed under the single gate electrode. A memory function implemented by these two charge holding portions and a transistor operation function implemented by the gate insulating film is separated from each other for securing sufficient memory function as well as easily suppressing short channel effect by making the gate insulating film thinner.

Abstract: An IC card includes a data memory portion (503) having a plurality of storage devices. The data storage devices each has: a semiconductor substrate, a well region provided in a semiconductor substrate, or a semiconductor film disposed on an insulator; a gate insulating film formed on the semiconductor substrate, the well region provided in the semiconductor substrate, or the semiconductor film disposed on the insulator; a single gate electrode formed on the gate insulating film; two memory function parts formed on opposite sides of the single gate electrode; a channel region disposed under the single gate electrode; and diffusion layer regions disposed on both sides of the channel region. Incorporating a memory using the storage devices, which allow further miniaturization, provides an IC card at low cost.

Abstract: A characteristic evaluating method of precisely obtaining a resistance value of an offset region in a semiconductor memory element constructed so that the resistance value of the offset region positioned below a memory function element formed on one side or both sides of a gate electrode changes according to an amount of charges or a polarization state of charges accumulated in said memory function element includes: a step of obtaining each of a resistance value between two diffusion regions inclusive formed on both sides of a channel region disposed just below the gate electrode of the semiconductor memory element via a gate insulating film, a resistance value of the channel region, and a resistance value of the diffusion regions; and a step of calculating the resistance value of the offset region which isolates the channel region and the diffusion region from each other on the basis of a result of subtracting the resistance value of the channel region and the resistance value of the diffusion regions from t

Abstract: The present invention provides a method of programming, into a computer, a memory array having a plurality of memory cells, including a verification step 1 of verifying whether a memory cell has been already programmed or it has not been programmed yet per memory cell to be programmed, a flagging step 2 of flagging the memory cell in the case where it is verified that the memory cell has not been programmed yet in the several verifying steps, to which the memory cell is subjected thereafter, even if it is verified that the memory cell has been already programmed, a first application step 3 of applying a programming pulse having a programming level to the not-programmed memory cell without any flag, a repeat step 4 of repeating the verification step 1, the flagging step 2 and the first application step 3 until it is verified that all of the memory cells have been already programmed at least once, and a second application step 5 of applying a boost pulse having a boost programming level lower than that of the p

Abstract: A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors (223) are formed on a P-type shallow well region (212). The depth of a shallow device isolation region (214) on the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep device isolation region (226) and the N-type deep well region (227).

Abstract: A semiconductor memory device includes a first nonvolatile memory cell, a bit line connected to the first nonvolatile memory cell, and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period “a” of time in response to transition of an input address signal. The first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: The present invention provides a semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, a user interface circuit including a command queue having a logic circuit for accepting commands issued by an external user and generating a program memory address, and an array control circuit having a microcontroller and a program memory for storing therein an execution code, and executing an operation on the memory cell array, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements. Each memory element comprises a gate electrode, a channel region, first and second diffusion regions, and first and second memory function sections provided an opposite aides of the gate electrode and having a function of retaining charges. The device further comprises a row decoder for selecting a word line in accordance with a row address, and a write control circuit for applying a write pulse to a bit line, which is connected to one of the first and second diffusion regions of the memory element connected to the selected word line, in accordance with a column address.

Abstract: A semiconductor storage device is provided with a gate electrode, a semiconductor layer, a gate insulating film sandwiched between the gate electrode and the semiconductor layer, a channel region under the gate electrode, diffusion regions provided respectively on two sides of the channel regions and being of the other conductivity region than the channel region, memory elements 1 provided respectively on two sides of the gate electrode and having a function of holding charges, and a word line driver circuit, in which the CMOS technique is used. The driver circuit includes a common node for supplying a potential for activating an output inverter for driving a row word line. While the semiconductor storage device is in a read mode, a CMOS inverter other than the output inverter controls a signal at the common node, the CMOS inverter connected to a read input line.

Abstract: A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane.

Abstract: A semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements are arranged and a program verify circuit 30. The memory element 1, 33 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on opposite sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies 109 that are located on opposite sides of the gate electrode 104 and have a function of retaining electric charge. A program load register 32 of the program verify circuit 30 eliminates a state that a memory element 33 which has initially been verified as having been correctly programmed needs to be further programmed.

Abstract: The present invention provides a semiconductor memory device including: a memory cell array in which memory cells are arranged; a plurality of terminals for accepting commands issued by an external user; a command interface circuit for interfacing between the external user and the memory cell array; a write state machine for controlling the programming and erasing operations; and an output circuit for outputting an internal signal to the plurality of terminals, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.