Abstract: A semiconductor memory device including memory cells, each memory cell including: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film; a channel region located below the gate electrode; a pair of source and drain regions arranged on a both sides, respectively, of the channel region, the source and drain regions having a conductive type opposite to that of the channel region; and memory functional units located on opposite sides, respectively, of the gate electrode, each memory functional unit including a charge retaining portion and an anti-dissipation insulator, the charge retaining portion being made of a material serving to store charges, the anti-dissipation insulator serving to prevent the stored charges from being dissipated by separating the charge retaining portion from both the gate electrode and the substrate, wherein a distance between a side wall of the gate electrode and a side of the charge retaining portion facing each other (T2) is ad

Abstract: A semiconductor memory device includes a memory array; a storage section that receives a maximum pulse value from a user of the semiconductor memory device; a control section that executes a writing processing or an erasing processing for the memory array and restarts the writing or erasing processing in the case where the processing for the memory array has failed; a counter section that counts up a number of processings performed by the control section; and a detection section that detects when the number of processings is equal to the maximum pulse value to prevent the control section from restarting the writing or erasing processing.

Abstract: A programming verification method of verifying programming of a nonvolatile memory cell, the method comprising at least the steps of: selecting first, second, . . . and n-th references corresponding to first, second, . . . and n-th threshold voltages specifying lower limit values of states 1, 2, . . .

Abstract: A semiconductor memory device includes a control logic circuit for generating read selection signals each selecting one plane for reading and write selection signals each selecting one plane for writing from a plurality of planes in which memory cells are arranged in an array, an address selection circuit disposed for each of the planes, and an address buffer circuit for simultaneously providing a write address and a read address. Each of the address selection circuits is configured so as to be able to receive one of the read selection signals and one of the write selection signals from the control logic circuit.

Abstract: A semiconductor memory device includes a first nonvolatile memory cell, a bit line connected to the first nonvolatile memory cell, and a control circuit connected to the first nonvolatile memory cell and the bit line, and disposed and configured in such a manner as to reset the bit line to a predetermined first potential state only for a certain period “a” of time in response to transition of an input address signal. The first nonvolatile memory cell has a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A semiconductor memory device comprising: (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundan

Abstract: This invention is a method of improving a data retention ability of a semiconductor memory device having a plurality of nonvolatile memory cells storing a plurality of memory states. The method includes the steps of: (a) selecting the nonvolatile memory cells in a first memory group each of which accumulates charges higher in level than a first threshold from the plurality of nonvolatile memory cells; (b) extracting the nonvolatile memory cells in a first sub-group each of which accumulates the charges lower in level than a second threshold from the nonvolatile memory cells in the first memory group; and (c) programming the nonvolatile memory cells in the first sub-group until each of the nonvolatile memory cells accumulates the charges higher in level than the second threshold.

Abstract: A semiconductor memory device includes: a plurality of nonvolatile memory cells; a first load cell for generating a read voltage relative to a read current during reading from a selected nonvolatile memory cell; a reference cell for storing a reference state corresponding to a reference current of the selected nonvolatile memory cell; a second load cell for generating a voltage based on the reference current through the reference cell; and a programming circuit for generating a reference voltage equal to a voltage obtained from a specific current-voltage characteristic of the first load cell with respect to the reference current and programming the reference cell so as to equalize the voltage of the second load cell with the reference voltage, thereby to compensate for variations in the first load cell.

Abstract: A method of verifying programming of a nonvolatile memory cell to a desired state, the method comprising the steps of: selecting first and second references respectively corresponding to first and second voltages; applying a programming voltage to the memory cell; sensing a threshold voltage level of the memory cell; and comparing the sensed threshold voltage level with the first and second references and, in the case where the threshold voltage level is higher than the first reference and lower than the second reference, indicating that the memory cell is programmed into the desired state, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region formed below the gate electrode, a source and a drain as diffusion regions formed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of re

Abstract: A display driver includes a display driving part for receiving image data and outputting a drive signal to a display panel; a nonvolatile memory part for storing control information for controlling output of the display driving part; and a control part for controlling output of the display driving part on the basis of the control information, wherein the nonvolatile memory part has a nonvolatile memory cell, and the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function for retaining charges.

Abstract: A semiconductor memory device including: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

Abstract: A semiconductor memory device includes: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges, wherein each of the diffusion regions has: a high-concentration impurity region disposed so as to be offset from the gate electrode; and a low-concentration impurity region disposed in contact with the high-concentration impurity region so as to overlap with the gate electrode, and an amount of current flowing from one of the diffusion regions to the other diffusion region is changed when a voltage is applied to the gate electrode in accordance with an amount of charges retained in the memory functional units.

Abstract: The present invention provides a method of programming, into a computer, a memory array having a plurality of memory cells, including a verification step 1 of verifying whether a memory cell has been already programmed or it has not been programmed yet per memory cell to be programmed, a flagging step 2 of flagging the memory cell in the case where it is verified that the memory cell has not been programmed yet in the several verifying steps, to which the memory cell is subjected thereafter, even if it is verified that the memory cell has been already programmed, a first application step 3 of applying a programming pulse having a programming level to the not-programmed memory cell without any flag, a repeat step 4 of repeating the verification step 1, the flagging step 2 and the first application step 3 until it is verified that all of the memory cells have been already programmed at least once, and a second application step 5 of applying a boost pulse having a boost programming level lower than that of the p

Abstract: A hearing aid comprising a data memory includes a plurality of semiconductor memory cells. The semiconductor memory cell has a gate insulating film formed on a semiconductor substrate, on a well region provided in the semiconductor substrate, or on a semiconductor film deposited on an insulator; a single gate electrode formed on the gate insulating film; two memory functional units formed on both sidewalls of the single gate electrode; a channel formation region formed under the single gate electrode; and first diffusion regions disposed on both sides of the channel formation region. The semiconductor memory cell is constituted so as to change an amount of currents flowing from one of the first diffusion regions to the other first diffusion region according to an amount of charges retained in the memory functional unit or a polarization vector when a voltage is applied to the gate electrode.

Abstract: A semiconductor memory device has a malfunction prevention device and a nonvolatile memory.

Abstract: A semiconductor memory device includes a nonvolatile memory section; and a volatile memory section, wherein the nonvolatile memory section includes a nonvolatile memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function for retaining charges.

Abstract: A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges. The method includes the steps of: selecting a row line connected to the gate electrode of a memory cell to be selected; grounding a first column line connected to the source of the memory cell to be selected; and applying a first potential to a second column line and a second potential to a third column line at the same time.

Abstract: A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell.

Abstract: A computer system comprising: (A) a CPU; (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors; (ii) a charge pump; (iii) a plurality of switching circuits; and (iv) logic circuitry; and (C) a system bus, wherein each of the side-wall memory transistors comprises: a gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional units formed on the both sides of the gate electrode and having a function of retaining charges.

Abstract: A gate electrode sidewall conductive film 120 is formed via a gate electrode sidewall insulation film 119 on a sidewall of a gate electrode 118. By properly removing this gate electrode sidewall conductive film 120 by anisotropic etching that has selectivity to the gate electrode sidewall insulation film 119, isolation between a source region and a drain region and formation of local interconnections by the gate electrode sidewall conductive film 120 are concurrently achieved. Further, the gate electrode 118 is also properly removed by etching that has selectivity to the gate electrode sidewall insulation film 119, and therefore, the gate electrode interconnection is concurrently formed. Through the above process, there can be provided an SRAM device, which is allowed to have high integration by shrinking the memory cell area with simplified interconnections.