Abstract: A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes (i) a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, (ii) a channel region provided under the gate electrode, (iii) diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and (iv) memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit includes an addressing arrangement for a single chip memory including cells associated with a plurality of redundant lines. A decoder for selecting a redundant row is selected by an address signal, and the decoder is programmed.

Abstract: There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

Abstract: A semiconductor storage device comprises memory function bodies that are formed on sidewalls of gate electrode located on one side and the other side of source/drain diffusion regions and have a function to retain electric charge or polarization. A quantity of electric charge flowing in a channel region changes depending on an amount of an electric charge or polarization retained in the memory function body specified by selecting a prescribed word line and a first bit line and a second bit line.

Abstract: A semiconductor storage element has a memory function body on opposite sides of a gate electrode formed on a semiconductor substrate. Each end of source/drain regions is located in the semiconductor substrate just under the memory function body and offset with respect to an edge of the gate electrode in a gate length direction to improve efficiency of electric charge injection into the memory function body. A storage state in the memory function body is found by detecting a amount of current between the source/drain regions, which current changes depending on the amount of the electric charge retained in the charge retention portion.

Abstract: A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

Abstract: A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising a plurality of memory elements, a section for performing an erase or program operation with respect to the memory array, a section for receiving a suspend command, and in response to the suspend command, suspending the erase or program operation, and a section for receiving a resume command, and in response to the resume command, resuming the suspended erase or program operation. Each of the plurality of memory elements comprises a gate electrode provided via a gate insulating film on a semiconductor layer, a channel region provided under the gate electrode, diffusion regions provided on opposite sides of the channel region and having a conductivity type opposite to that of the channel region, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.

Abstract: A semiconductor storage device is provided, which comprises a memory array comprising memory elements, a write state machine for applying a first voltage for performing a write or erase operation, with respect to one of the memory elements, to the memory element via a bit line connected thereto, and thereafter, applying a second voltage for verifying whether or not the write or erase operation has been performed, to the memory element via the bit line, and a reset portion for grounding the bit line connected to the memory element after the write state machine has applied the first voltage and before the write state machine has applied the second voltage. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor memory device includes a memory cell array in which plural memory cells are arranged, a memory operation circuit, connected to the memory cell array, for executing a memory operation on the memory cell array, and a command controller, connected to the memory operation circuit, for receiving a command from the outside and generating a predetermined control signal to the memory operation circuit on the basis of the received command to control execution of the memory operation by the memory operation circuit. The memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

Abstract: A semiconductor storage device to provided, which comprises a memory array comprising memory elements, a write state machine for performing a sequence of a program or erase operation with respect to the memory array, a decoder for decoding a signal indicating a current state of the write state machine, which is output from the write state machine, and outputting a status signal indicating a status of the program or erase operation with respect to the memory array, a status register for storing the status signal, and an output circuit for outputting the status signal stored in the status register. Each memory element comprises a gate electrode, a channel region, diffusion regions, and memory function sections provided on opposite sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor switching element and a semiconductor storage element each have a gate electrode, a pair of source/drain regions and a channel forming region. Memory function bodies having a function of storing electric charges are provided on opposite sides of the gate electrode of the semiconductor storage element. In the semiconductor storage element, an amount of current that flows from one of the source/drain regions to the other of the source/drain regions upon application of a voltage to the gate electrode is variable depending on an amount of electric charges retained in the memory function body.

Abstract: A semiconductor memory device includes a memory cell including a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; a switching transistor circuit including a negative voltage switching circuit for applying a negative voltage to the gate electrode of the memory cell, and a switching transistor connected to an output of the negative voltage switching circuit and a first voltage source for outputting a voltage having a voltage level lower than zero volt; a pull-up circuit connected to a control terminal of the switching transistor and selectively connected to a second voltage source for outputting a voltage having a voltage level higher than zero volt; and a pull-down circuit connected to the f

Abstract: A semiconductor storage device includes a field effect transistor having a gate insulator, a gate electrode and a pair of source/drain diffusion regions which are formed on a semiconductor substrate. Recesses are formed so as to increasingly widening sideways in cross section between opposite side portions of the gate electrode and the semiconductor substrate surface, respectively. Memory function bodies each of which is composed of a charge retention part made of a material having a function of storing electric charge, and an anti-dissipation dielectric having a function of preventing dissipation of stored electric charge, are formed on opposite sides of the gate electrode in such a fashion that the recesses are thereby buried. Thus, the semiconductor storage device is capable of solving the issues of overerase and read failures due to the overerase and enhancing the reliability.

Abstract: A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

Abstract: A semiconductor memory device of the present invention includes a first memory array, a first address register for storing therein a first address of the first memory array, a second memory array, a second address register for storing therein a second address of the second memory array, a multiplexer connected to the first memory array and the second memory array and to a memory output unit for selectively outputting the first memory array or the second memory array, and an array selection circuit for selecting the first memory array for re-programming in accordance with an input address and selecting the second memory array for a reading operation. The array selection circuit sends the first address to the, first address register, sends the second address to the second address register, and further, controls the multiplexer, so as to allow the second memory array to be connected to the memory output unit during re-programming of the first memory array.

Abstract: A semiconductor memory includes: a p-type semiconductor (p-type semiconductor film on a substrate, a p-type well region in a semiconductor substrate, or an insulator); a gate insulating film formed on the p-type semiconductor; a gate electrode formed on the gate insulating film; two charge storage sections formed on side walls of the gate electrode; a channel region provided below the gate electrode; and a first n-type diffusion layer region and a second n-type diffusion layer region provided to sides of the channel region, wherein: the charge storage sections are arranged to change an electric current flow between the first n-type diffusion layer region and the second n-type diffusion layer region under application of a voltage to the gate electrode according to the quantity of electric charges stored in the charge storage sections; and the first n-type diffusion layer region is set to a reference voltage, the other n-type diffusion layer region is set to a voltage greater than the reference voltage, and the

Abstract: A method for programming a nonvolatile memory cell includes the steps of: applying a first pulse to a nonvolatile memory cell to accumulate a first amount of charge which is smaller than a target amount of charge; in the case where the accumulated first amount of charge is smaller than a second amount of charge, applying a second pulse train to the nonvolatile memory cell, so that charges in an amount close to the second amount of charge are accumulated in the nonvolatile memory cell; when the nonvolatile memory cell is determined as retaining charges larger than the second amount of charge, applying a third pulse train until charges within an allowable error range of the target amount of charge is stored in the memory cell.

Abstract: A semiconductor memory device includes a controller for programming a nonvolatile memory cell by applying a first pulse so that a first amount of charge which is smaller than a target amount of charge is accumulated in the nonvolatile memory cell, a second pulse train of pulses so that a second amount of charge which is smaller than the target amount of charge and larger than the first amount of charge is accumulated in the nonvolatile memory cell, a third pulse train of pulses so that a third amount of charge which falls within an allowable error range of the target amount of charge is accumulated in the nonvolatile memory cell.

Abstract: A semiconductor memory device includes a field-effect transistor provided on a surface of a P-type transistor substrate. The field-effect transistor includes two N-type diffusion layer regions, a gate electrode, and a charge storage section. By applying a reference voltage to one of the N-type diffusion layer regions, a voltage higher than the reference voltage to the other of the N-type diffusion layer regions, a voltage lower than the reference voltage to the gate electrode, and a voltage higher than the reference voltage to the P-type semiconductor substrate, holes are injected into the charge storage section. Because the forward voltage is applied to a PN junction between one of the N-type diffusion layer regions and the P-type semiconductor substrate, it is possible to inject the holes into the charge storage section at the voltages lower than the voltages required if the forward voltage is not applied. Therefore, it is possible to decrease operating voltages of the semiconductor memory device.